I have a -600, and to tell you the truth, I wouldn't have rejected a board
if I saw figure 295c. Which does bring up a complaint about the photos they
put in the standards. There are a lot of times that a photo is placed in
the standards and the time is taken to label the photo like this one
labeled as Figure 295c, but no where is that photo referenced in the text
of that section. So a lot of times I get asked by my operators what the
photo is showing? Is it a defect? Is it a process indicator? Exactly what
is IPC showing?

Steve

On Mon, Apr 15, 2019 at 9:07 AM Stadem, Richard D <[log in to unmask]>
wrote:

> Hi, Wayne
> Your post is hard to understand, and since I do not have a copy of
> IPC-600  handy to reference what it says and see the pictures, I cannot
> help you. Not all of us have access to every standard within IPC.
> I do wish I could help you. Sorry.
> dean
>
> -----Original Message-----
> From: TechNet <[log in to unmask]> On Behalf Of Wayne Thayer
> Sent: Monday, April 15, 2019 8:46 AM
> To: [log in to unmask]
> Subject: Re: [TN] Solder mask chipping on board edge
>
> I haven't received a single comment on this post. Was it held up by the
> system or the moderator?
>
> On Thu, Apr 11, 2019 at 5:58 PM Wayne Thayer <[log in to unmask]>
> wrote:
>
> > Gentlemen-
> >
> > What the dickens is going on with IPC-A-600 Section 2.9.5? The
> > "Nonconforming" snapshot at the bottom shows a bit of soldermask
> > chipping due to the designer neglecting to clear the engraved area for
> the "V-score"
> > process. The chipped mask exposes no conductors and does not decrease
> > the protected distance between any conductors. The edges of the
> > through-hole pads are already exposed due to the soldermask backoff.
> >
> > I tried to work through the IPC requirements which should cover this
> > case and I can't find any other than this explanatory picture book.
> > The only explanatory statement is that this applies "when the design
> > requires coverage to the printed board edge." Sounds like an unusual
> > requirement for this situation, given that a "V-score" makes a sloping,
> messy edge anyway.
> >
> > Is the convention that, because this silliness got into the document,
> > if some lazy layout guy neglects to clear the path for the "V-score",
> > that it is then presumed that "the design requires coverage to the
> > printed board edge?" That'd be pretty ridiculous since if the lazy
> > layout guy forgot to clear the mask, you can be certain they aren't
> > going to bother creating a special note directing the fabricator to
> ignore his laziness.
> >
> > Wayne Thayer
> >
>


-- 
Steve Gregory
Kimco Design and Manufacturing
Process Engineer
(208) 322-0500 Ext. -3133

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