Mail*Link(r) SMTP               FWD>ASY: external high-voltage testing

Hello [log in to unmask],

I read into you inquiry, you have concerns about the actual probing and
electrical testing of printed board electronic assemblies, and electrical
spacing requirements.

The simple one first, the electrical spacing requirements for SMT are the same
as for IMT (insertion mounted technology).  As we know, mother nature has
established certain set of physiscal/electrical material capabilities to
withstand high voltage (HV) electrical  stresses.  Exceed the rules and we'll
have a failure and it doesn't care what type of technology we are using.  The
more we stress the rules, the greater the probability of a functional failure
the more "robust" (conservative) our design, in general, the less prone to
failure and more reliable -- nothing new to us.  Electrical spacing between
conductors is based on the applicable voltage requirements (test/use),
dielectric strength of the solid/liquid/gas dielectrics, and the quality of
the dielectrics.

Probing can become a problem as the conductor spacings become smaller,
high-voltage (HV) probing / fixturing (> a few kV) becomes more difficult with
a gas dielectric because more frequently the breakdown at test voltages will
be from the test probes/connections or near by conductive materials and not
between the conductive patterns on the printed surface of the PB.  So, some
consideration must be given to performing HV testing in a liquid.  Then after
testing is completed, the assembly is encapsulated/potted with primary
dielectric(s).

Generally, when SMT is linked with HV, some designers feel all of the
electrical spacing requirements go-away for electrical creepage and clearance
spacing requirements -- they don't.  Then some designers feel they can do a
simple "conformal coating" and their problems will go away -- they might for
some applications, but ie more frequently is a stay-of-execution (latent
failure) for most others.  The electrical spacing requirements for both
printed boards and printed board electrical/electronic assemblies are
contained in IPC's-D-275, Table 3-1; and yes, they are conservative, but
they've withstood the tests of time and have proven to be reliable for a wide
range of applications and operating environments.

Bottom thoughts for HV designs:  consider both dc and ac (direct and
alternating current) in the HV application design requirements, the electronic
packaging design's packaging density (spacing) requirements will drive whether
you can use solid/liquid/gas (or a combination thereof) as your primary
insulation dielectrics; and the design must control the "effective" insulation
between conductors in all HV applications, under all intended (and unintended)
test/use/operating environments. 

Ralph Hersey
[log in to unmask]
  


--------------------------------------
Date: 8/14/96 9:01 AM
From: [log in to unmask]
Does anyone happen to have any information on possible external high-voltage
testing and spacing requirements pertaining to SMT packaging?  Are there any
industry solutions to high-voltage problems?

[log in to unmask]

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