Thad;
I will look into placing a reference table depicting typical minimum dams
achievable with the various types of solder mask materials. However, mask
suppliers continually enhance their products, as well as board fabricators
enhancing their capability to apply the materials. This leads to a reference
table that becomes quickly outdated.
On the other hand, good design practice takes into account mamnufacturing
tolerances. Using your example, with the BGA, the designer should recognize
that he/she has not left enough space for a sufficient dam, after
considering the manufacturing tolerances. The board manufacturer, upon
completing his DRC's should notify you that there is a problem meeting the
specifications I previously mentioned.
I summary, there is no problem allowing the fabricator to resize the mask to
meet his process, the applicable design standard, and the applicable
performance standard, as long as the designer has done his/her homework.
At 05:12 PM 5/13/96 CST, Thad McMillan wrote:
> Gary,
>
> Thanks for the reply. Speaking as a OEM we typically don't like
> our suppliers to modify soldermask because there are situations when
> this can hurt us.
>
> Take an example of two adjacent soldermask opennings associated
> with a BGA pad and its' via. If a supplier increases the associated
> soldermask openning on both the BGA and its' via then the Soldermask
> web between the pad shrinks. If the web becomed too thin we will get
> BGA solder down the adjacent via at assembly resulting in a bad joint.
>
> Sometimes at layout we need to know what is possible. For example
> if we lay out a board with 5/5 outers. If we put traces within 5 mils
> of a adjacent SMT or test pad there is not enough room for soldermask
> clearance on both the pad and the and trace. Either the trace will be
> exposed or the pad will be. This results in disaster at through hole
> assembly. Sometimes larger spacing is needed on outers between traces
> and pads to account for soldermask misregistration.
>
> It would be great to get add to our design standards a table that
> gives minimum soldermask design clearance and web for various types of
> soldermask.
>
> My question below is for both standard LPI mask and thin LPI.
>
> Regards,
>
> [log in to unmask]
>
>
>______________________________ Reply Separator
_________________________________
>Subject: Re: FAB: Soldermask Clearance and Web Width requirements
>Author: Gary Ferrari <[log in to unmask]> at Dell_UNIX
>Date: 5/13/96 3:31 PM
>
>
>Thad;
>
>You need to state whether you want numbers for LPI, high conformance thin
>films (<0.002inch thick), or both.
>
>The IPC standards recommend that you send 1/1 data to the fabricator, with
>your requirements as to encroachment on the lands. If you specify IPC-RB-276
>and IPC-SM-840, the encroachment issue will be covered. In short:
>
>IPC-RB-276, Para. 3.11.1
>
>d. Solder resist need not be flush with the periphery of the land. Clearance
>of solder resist around a land exposing bare laminate may average up to 0.13
>mm [0.005 in] but shall not expose isolated lands. Misregistration may allow
>the bare area between lands and conductors to have no solder mask; however,
>the adjacent conductor shall not be exposed. Misregistration may allow
>clearances to vary so that while the average of 0.13 mm [0.005 in] is
>maintained on opposite sides of a given land, the clearance may range from
>0.25 mm [0.010 in] to 0.000 mm [0.000 in].
>
>f. When a land contains no plated through holes, as in the case of surface
>mount lands, misregistration shall not cause encraochment of the solder
>resist over the land greater than 0.05 mm [0.002 in] for pitch of 1.25 mm
>[0.050 in] or greater; and encroachment shall not exceed 0.025 mm [0.001 in]
>for pitch less than 1.25 mm [0.050 in]. encroachment may occur on adjacent
>sides but not on opposite sides of a surface mount land.
>
>The reasoning behind 1/1 data is that each fabricator's capability is
>different. However, THEY know what they need to do to meet the end product
>requriemetn. They will compensate the data for their process.
>
>
>At 09:49 AM 5/13/96 CST, Thad McMillan wrote:
>> Designing soldermask webs is always a pain in the neck, particularly
>> for fine pitch.
>>
>> I'd like to conduct an informal survey, supplementing Doug's excellent
>> questions below regarding soldermask:
>>
>> 1. Using LPI type masks what is the minimum nominal clearance
>> (Copper to soldermask) that PCB fabricators need to prevent soldermask
>> from encroaching onto the copper? I've got answers in the past
>> ranging from 2 mils to 5 mils.
>>
>> 2. What is the minium nominal soldermask design web width that can
>> maintained in production? I.E. a minimum width that I can expect to
>> still have a soldermask web remaining after processing. I've got
>> answers here in the past also from 2 - 5 mils.
>>
>> Need both answers from as many fabricators as possible.
>>
>> I am looking for a number suitable for volume production (i.e. >10K
>> panels per month).
>>
>> Does a table exist in any IPC design guidelines indicating these
>> geometries?
>>
>> Is it typical practice for PCB fabricators to modify soldermask
>> artwork to get the necessary clearance?
>>
>> Thanks,
>>
>> [log in to unmask]
>>______________________________ Reply Separator
>_________________________________
>>Subject: FAB: Soldermask Webs.
>>Author: [log in to unmask] at Dell_UNIX
>>Date: 5/11/96 7:50 AM
>>
>>
>>-- [ From: Doug Jeffery * EMC.Ver #2.10P ] --
>>
>>Friends,
>>
>>We have seen many designs that have smaller webs between SMP's than they
>>have circuits. Imagin creating a .003" line in Soldermask yet the board
>>has .006" traces. We have found that any Soldermask web design that is
>>.005" of web by design is reproducable and can be placed reliably, but
>>below .005" the LPI masks do no hold on.
>>The key reason is undercut. The LPI between SMP's is thicker than
>>anywhere else on the board. This requires that the exposure be set up
>>to accomadate the thicker material, however overexposure can cause
>>other feature problems. After you have optimised the exposure you play
>>with the developing until you keep a good dam between pads, Bingo you
>>are leaving ink in the holes. So, you crank up the developer and get
>>that ink out of the holes....Catch 22...
>>
>>AT .005" feature size (dams) you are able to optimize the process,
>>below .005" dams the undercut takes the foot of the LPI down to .003"
>>or .002" which makes the adhesion a problem, hense the peelers and
>>redoposit problems that you expressed.
>>
>>?What is the answer for .020" pitch devices that require .014" pad
>>widths?
>>
>>?what is the answer for .006" lands on .012" centers?
>>
>>I don't know but certainly we have to get to one. We have tried double
>>coating, Unpigmented material, reduced pigmented material..No
>>significant result differences. We try to get customers to leave use
>>.009" min space between SMP's to keep a dam (2/5/2 by design. This
>>makes LPI exposing a tighter regitration than our outerlayer
>>requirements.
>>
>>
>>
>>
>Regards,
>
>Gary Ferrari
>Tech Circuits
>(203)269-3311
>[log in to unmask]
>
>
>
Regards,
Gary Ferrari
Chairman IPC-D-275
Tech Circuits
(203)269-3311
[log in to unmask]
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