TECHNET Archives

September 1998

TechNet@IPC.ORG

Options: Use Monospaced Font
Show Text Part by Default
Show All Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
Subject:
From:
David D Hillman <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Thu, 10 Sep 1998 19:32:47 -0500
Content-Type:
text/plain
Parts/Attachments:
text/plain (106 lines)
Hi Ed - I think a little bit of JSTD-003 explanation will be helpful which
will change how you view the situation you are facing. The Wave Solder Test
(test method D, paragraph 4.2.4) does not require complete hole fill of the
plated thru holes being tested - it only requires ".....The specimen has
soldered successfully if solder has risen in all the plated thru holes. The
solder shall have full wetted the walls of the hole." so the holes being
tested can have some depression rather than being completely filled in a
physical sense. Take a look at JSTD-001 table 9-2, page 18, example E and
you'll see what I mean of a plated thru hole having a depression but is a
filled hole.  The Wave Solder Test is an applications test rather than a
benchtop/laboratory test which means a number of other variables become
part of the testing methodology. This is the reason that the Wave Solder
Test description contains a number of issues that must be "agreed upon by
the vendor and the user". The type of flux, the wave solder machine
configuration, the temperature recipe, etc. all will have an impact on the
holes filling - it turns into the soldering-ability versus solderability
argument. The test board could be very solderable but a processing variable
influence could result in a hole not filling. If a test board contained
hundreds of holes and only a couple didn't fill then I would accept the
board (unfortunately I'm not your customer so you still have an situation).
Many folks don't realize but when using the suggested 40 hole coupon found
in figure 3a of JSTD-003 if only 38 of 40 holes fill with solder then 95%
of your holes filled - and the industry has used the 95% criteria for
solderability testing for a number of years.  Also you pointed out that
there are no component leads in the holes - leads definitely improve solder
flow within the plated thru holes.  I suggest that you and your customer
take a look at his/her wave solder process, work through defining the
variables for the boards that are being questioned. That way everyone can
understand the limitations and expectations of what the Wave
Solder Test is showing in terms of solderability results.  Good Luck.

Dave Hillman
JSTD-003 Chairman
[log in to unmask]

P. S. I also noticed that the statement ".... a smaller percent coverage
may be determined...."  found in the surface pad evaluation criteria for
the Wave Solder Test is not found in the plated thru hole evaluation
criteria. I believe this is an oversight and will submit a comment for a
change to the current specification revision process currently underway on
JSTD-003.





Ed Cosper <[log in to unmask]> on 09/10/98 04:03:18 PM

Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond
      to Ed Cosper <[log in to unmask]>

To:   [log in to unmask]
cc:
Subject:  [TN] solderability testing




Hi all,

Just a quick question. As a board manufacture we typically perform a
solderability test ( solder float ) on a small piece cut out of a board
that has at least 30 holes. Customers many times will
run a complete bare board thru the wave to check solderability. I have a
situation with one customer that I has frequent rejections because one or
two holes out of hundreds do not fill during the wave of the bare boards.
All of my solder float tests pass and samples fromt the same lots rejected
ran over someone elses wave solder fine.

I would like to know what most people would accept on that type of
solderability test. Specifically regarding instances of when one or two
isolated holes fail to fill out of several hundred holes on a 5x8 board. I
really do not know if I should expect all holes to fill 100% without leads.
Is there a specific specification that covers wave solder tests on complete
bare boards?

Any help would be appreciated.

Ed Cosper

################################################################
TechNet E-Mail Forum provided as a free service by IPC using LISTSERV 1.8c
################################################################
To subscribe/unsubscribe, send a message to [log in to unmask] with following
text in the body:
To subscribe:   SUBSCRIBE TechNet <your full name>
To unsubscribe:   SIGNOFF TechNet
################################################################
Please visit IPC's web site (http://www.ipc.org) "On-Line Services" section
for additional information.
For technical support contact Hugo Scaramuzza at [log in to unmask] or
847-509-9700 ext.312
################################################################

################################################################
TechNet E-Mail Forum provided as a free service by IPC using LISTSERV 1.8c
################################################################
To subscribe/unsubscribe, send a message to [log in to unmask] with following text in the body:
To subscribe:   SUBSCRIBE TechNet <your full name>
To unsubscribe:   SIGNOFF TechNet 
################################################################
Please visit IPC's web site (http://www.ipc.org) "On-Line Services" section for additional information.
For technical support contact Hugo Scaramuzza at [log in to unmask] or 847-509-9700 ext.312
################################################################


ATOM RSS1 RSS2