TECHNET Archives

January 2018

TechNet@IPC.ORG

Options: Use Monospaced Font
Show Text Part by Default
Show All Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
Subject:
From:
David Hillman <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, David Hillman <[log in to unmask]>
Date:
Mon, 8 Jan 2018 14:45:38 -0600
Content-Type:
text/plain
Parts/Attachments:
text/plain (70 lines)
Hi Stephen  - the next revision of the IPC-7093 BTC standard contains a
huge amount of updated information on reducing voiding, solder paste
deposition patterns, use of soldermask for dam/direction purposes. I would
get a copy of the working draft when its released as there is so good stuff
in the works on that topic. I am guessing the standard will be going to
ballot later this year.

Dave

On Mon, Jan 8, 2018 at 11:56 AM, Vargas, Stephen M <
[log in to unmask]> wrote:

> I'm assuming that a ramp, soak, spike profile will reduce voiding as
> opposed to a ramp to spike. I was wondering however if anyone has done any
> experiments (void reduction) with round apertures vs. square apertures in a
> windowpane pattern?  Thanks
>
> Regards,
> Steve Vargas
>
>  Please consider the environment before printing this e-mail
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Bob Wettermann
> Sent: Monday, January 08, 2018 12:51 PM
> To: [log in to unmask]
> Subject: EXTERNAL: Re: [TN] solder voids - QFN belly pad
>
> Once the criteria is determined for the max voiding percentage the most
> common suspects we have found, from a process standpoint  are:
>
> 1. Type of paste / flux chemistry
>
> 2. Thermal Profile
>
> 3. Printing reduction in the center ground - ie the print pattern
>
> Certainly vias in the pad will cause the situation to be very complicated
> as well will very large center ground patterns relative to the part size.
>
> Bob Wettermann
>
>
> On Mon, Jan 8, 2018 at 10:26 AM, Guy Ramsey <[log in to unmask]> wrote:
>
> > We are having trouble with a lot of boards.
> > We are seeing excessive voids like the ones on page 18 of this
> > presentation.
> >
> > https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=
> > 0ahUKEwj27JnJ38HYAhUF5YMKHWYICvcQFggpMAA&url=https%3A%2F%
> > 2Fwww.eptac.com%2Fwp-content%2Fuploads%2F2012%2F06%2Feptac_
> > 07_18_12.pdf&usg=AOvVaw2OX6J_YRqkuNUNNgDBvmwZ
> >
> >
> > The vias are filled and plated. Anyone seen this, resolved it?
> >
> >
> > Guy
> >
>
>
>
> --
> Bob Wettermann
> BEST Inc
> [log in to unmask]
> Cell: 847-767-5745
>

ATOM RSS1 RSS2