Hi Ed --

I recently attended a seminar by Joe Keller, now a consultant, previously
head of PCB and PCBA FA lab at Motorola.  Joe presented evidence that a
full via may be less able to withstand thermal fatigue than a partially
filled via. His recommendation, don $B%? (Jt worry about it one way or the other.

Dan Babcock
Sr. Supplier Engineer
Maxtor Corp

>
>Date:    Mon, 15 Dec 1997 07:12:31 -0500
>From:    Ed Holton <[log in to unmask]>
>Subject: filling vias!
>
>Here is a general question to start out the week:
>
>Should the wave solder process be required to fill all the vias of a
double
>sided/plated thru board?  Why or why not?
>
>Is it a good practice to probe vias for the ICT test?  Why or why not?
>What is recommended?
>
>(Our boards are double-sided plated thru, but the annular ring of the via
>on the top side is covered with solder mask (not tented) and I am having
a
>heck of a time filling all the vias (98% success rate). The ICT probes
vias
>and we are having ICT failures due to unfilled vias and the probe method.
>The ICT probes are being switched to a larger tulip type head.  We
>inherited this design!!  A lunch (and bragging rights) between ICT and
>myself are on the line!)
>
>Ed Holton
>Hella Electronics
>313-414-0944
>

##############################################################
TechNet Mail List provided as a free service by IPC using LISTSERV 1.8c
##############################################################
To subscribe/unsubscribe, send a message to [log in to unmask] with following text in the body:
To subscribe:   SUBSCRIBE TECHNET <your full name>
To unsubscribe:   SIGNOFF TECHNET
##############################################################
Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional information.
For the technical support contact Dmitriy Sklyar at [log in to unmask] or 847-509-9700 ext.311
##############################################################