IMO, provided that the solder mask is intact, I have nothing against
from the electrical point of view for assemblies not requiring the
highest reliability under arduous conditions. On the other hand, from
the physical point of view, if the bottom side of a component is plane
and the solder mask is thick, it is clear that both component lands
cannot be pulled down in intimate contact with the copper, with just the
intermetallic layer in between. This I don't like. I feel that a very
thin solder mask is required under these conditions. FWIW

Brian

Park Matthew wrote:
>
> We want to place traces under 1206, 805 and low-profile SOT23 components.
> We are currently doing that for some designs and desginers are pushing for
> it even further.  I am against placing traces under these components because
> of greater potential for causing tomstoning, shorting possibilities, and not
> being a robust design.  What are your thoughts for this?  Is there any data
> or studies done to show it is ok or not ok to run traces under chip
> components.
>
> We ran a typical SMT process with LPI solder mask, water-soluble and
> no-clean (very soon) and reflowed using convection ovens.
>
> thanks
> Matthew S. Park
> Sr. Process Engineer
> Phoenix International Inc.  Fargo, ND.
> Tel: 701-282-9364, ext 434
> Fax: 701-282-9365
>
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