Not sure if this is the right forum this type of question but here it goes...

We have a small SMT PWA, 4 by 5 inches, 10 layer, 0.042 inch thick, I think
"standard" fr4? construction.  Numerous SOICs and a single 256pin PBGA plus
some discrete components on the topside, and only discrete components on
the bottomside.

We are developing a bed of nails in-circuit/functional electrical test for
the card.  The test engineer has located 550  6.5ounce probes on the
bottomside of the board (roughly 220 pounds of force total).  The board has
open vias so he has a clamshell type of fixture to constrain the top of the
board when the fixture is pulled down by vacuum on the tester.  There are
25 nylon fingers contacting the topside of the PWA.  The board rests on the
probes and nylon fingers during test.

When the vacuum is applied, the assembly does not sit flat.  You end up
with a very convoluted surface - the nylon fingers tend to be low spots.
Along the long edge I estimate the board has/had waviness equivilent to a
board thickness and a half peak to peak. After exercising a couple of
assemblies over the course of a few weeks, some of the BGA connections
became intermittent.  We did not perform a root cause failure analysis but
I suspect the board flexure during testing is the culprit, affecting the
solder joints or PWA interconnects.

The test fixture house tweaked the fixture so the board sits a little
flatter but I am still concerned.  The board in our experience is thin and
I worry about any flexure or stress on the PBGA connections.

Anyone with experience with board flexure induced failures, especially of
PBGAs?

Any real-world guidelines for how much flexure during in-circuit test is
OK?  I know we aren't going to get it perfectly flat but maybe we need to
re-think our fixture design to minimize the board stresses.

Any inputs appreciated.  Thanks.

-Gregg Klawson
GTE Governments Systems Corp
Taunton, MA, USA
telephone: +1.508.880.1822, email: [log in to unmask]