Mail*Link(r) SMTP FWD>more heavy copper...
Date: 7/9/96 5:03 PM
From: Jack Olson
Jack,
Hopefully this will help.
>As I was browsing through some previous discussions, I came across the
>following question (yeah, I'm quoting myself). It was regarding the use
>of Figure 3-4 in IPC-D-275 to determine an appropriate trace width based
>on current.
>> As an example, say I need 5amps and 20 degrees over ambient is a safe
>> assumption. The chart gives ABOUT 100 square mils, which corresponds to
>> ABOUT a 75mil trace width on the 1oz copper curve.
>> OK, how many of you use 75mils? How safe is this number?
For years we have used the charts in the ol' MIL-STD-275, and about 4 years
ago, we switched over to the IPC's-D-275. Most of these charts have
significant fudge-factors built into them to compensate for manufacturing
tolerances. There are problems with the IPC's current dimensional tolerancing
philosophy in using a percentage of conductor width as a design/manufacturing
tolerance. We take exception to the percentage tolerancing and put hard
numbers down for conductor width tolerancing. Why do we take exception, in
you case, a 20% tolerance on a 1.9 mm wide line (IMO) is atrocious; by my
math, that's a +/- 381 micrometers, if a printed board manufacturer has that
kind of an imaging and etching problem, IMO they're in the wrong business
(that is for 35 micrometer laminated foil + plating build up to about 70-80
micrometer Cu conductor thickness). By definition, the conductor width
tolerance would apply to a power/ground plane, if it were 600 mm wide/long,
the 20% tolerance would be 120 mm, by experience, most printed board
manufacturers have no problem in exceeding that tolerance. In comparison
though, a 20% tolerance on a conductor width of 25 micrometers is achieveable
and a challenge.
For many years, we have used a stepped conductor width tolerance with little
or no problems. When we converted over to full industry specifications for
all of our Class 2 printed board products, we place the following conductor
width dimensional tolerance chart on the product definition (master) drawing
(for 35 micrometer foil + 25 micrometer electroplating buildup).
Design Conductor Width(DCW) Tolerance
< 250 micrometers +/- 25 micrometers
0.250-1.27 mm 10 % of DCW
>1.27 mm +/- 13 micrometers
The PB Designers are supposed to add an additional tolerances for additional
Cu thicknesses.
I hope the following does not offend my IPC and technet's colleague's, but in
my experiences with printed boards, current carrying capacity is frequently a
very critical requirement in many of our applications, and so based on my
experiences, the following paragraph is worded and phrased the way it is.
Concerning the current carrying ability of conductive patterns. The conductor
width tolerance is more critical on the conductor's resistance (key item for
conductor I squared R power loss) for narrow conductors that conductor
thickness, in contrast, for wide (high current conductors) [ IMO -- if
your're not dumb enough to use the IPC 20% conductor width tolerance] then the
conductor thickness has more of an effect on the conductor's resistance and
therefore power loss.
>Many of you responded (THANK YOU) but one issue was never brought up and
>I am still curious about it.
>According to IPC-RB-275 Table 7, a conductor width can be reduced 20% by
>a nick or scratch for a length of 0.5 inches and still be acceptable,
>plating thickness can vary (as well as the 1oz copper stock), traces can
>be over-etched, etc.
I believe you're refering to IPC's-RB-276 not the 275. The November "94
amendment to 276 corrected the conductor width problems (IMO except for the
percent tolerancing). Paragraph 3.8.1 was changed to the minimum conductor
width to be "designed" and product conductor width is 100 micrometers.
Before, in the 276, the unless otherwise specified minimum conductor width was
100 micrometers, regardless of the designed conductor width. IMO that was
worse than the +/- 20 or 30%, because now a 600 mm wide conductive pattern
could be reduced to 100 micrometers. The conductor width tolerances are now
+/- 20% for Class 2 & 3, and +/- 30% for Class 1. There is no "length" 13 mm
restriction any more.
>So does the chart indicate that I should use 75mil aperture in my CAD
>system, or is my goal to take all factors into account and try to ensure
>the END RESULT is 75 mils minimum?
We have traditionally "printed" the production master drawings at the DCW and
have had no problems (except for very narrow conductor widths) in meeting
reasonable tolerances. For us, using our design and manufacturing conductor
width and manufacturing tolerances the 75 milinch wide conductor would have a
+/- 5 milinch tolerance, very reproduceable with 1 oz Cu foil + Cu plate, and
even more manufacturable if you use "thin-clad" and only "normal"
plated-through hole surface buildup (1-1.3 milinch).
>Am I splitting hairs? Jack
IMO no, you're not splitting hairs? -- you just want to know how to establish
design/manufacturing requirements to meet end-item (electrical) product
definition requirements.
Ralph Hersey, [log in to unmask]
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Date: Tue, 09 Jul 1996 16:25:25 -0700
From: Jack Olson <[log in to unmask]>
Organization: Circuit Packaging and Layout
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