Sorry for adding to distraction -- was commenting in reply to Dave's comment about filled uvias.
-----Original Message-----
From: TechNet <[log in to unmask]> On Behalf Of Jack Olson
Sent: Thursday, August 29, 2019 6:15 AM
To: [log in to unmask]
Subject: Re: [TN] [External] Re: [TN] TYPE III vs TYPE V vias
Thanks, but nothing in in my original post, proposed scenario, or follow-up questions is related to micro-vias (I'm trying to keep solder from dripping THROUGH a hole using the cheapest and most reliable method) interesting responses, though!
Jack
On Wed, 28 Aug 2019 17:45:18 +0000, Dwight Mattix <[log in to unmask]> wrote:
>Edit to add to my last post for uVia scenario:
>
>Yes, concur with Dave. Filled copper uVia. No call for working with fabs that do uVia with epoxy fill and overplate these days. If that is your fab's solution for filled uvia then (IMAO) find a better uVia fab.
>
>-----Original Message-----
>From: TechNet <[log in to unmask]> On Behalf Of David Hillman
>Sent: Wednesday, August 28, 2019 7:09 AM
>To: [log in to unmask]
>Subject: Re: [TN] [External] Re: [TN] TYPE III vs TYPE V vias
>
>Hi Jack - well, I am going to play Switzerland and agree with both Dave and Wayne! We utilized filled and plated shut microvias on a large number of board designs. The reason for using the plated shut microvias is to eliminate solder thieving and voids in BGA solder joints or the thermal pads on BTC components. So that is the voting with Dave side of the equation. We are successful because we have worked closely with our board fabricators to have consistent, reproducible fill and plate processes - as Wayne detailed, the process is not a trivial task and takes good process control and diligence (there is my Wayne side of the equation).
>
>Dave Hillman
>Collins Aerospace
>[log in to unmask]
>
>On Tue, Aug 27, 2019 at 5:49 PM Jack Olson <[log in to unmask]> wrote:
>
>> On Sat, 24 Aug 2019 10:55:55 -0700, Wayne Thayer
>> <[log in to unmask]>
>> wrote:
>>
>> >Dave,
>> >
>> >I beg to differ....
>> >
>> >Specifying caps when they aren't required by your application
>> >invites unnecessary risk.
>> >
>> >First, specifying anything which has no inherent benefit to the
>> >design is poor "systems engineering" practice.
>> >
>> >Second, plated caps aren't simply like asking for extra nuts on your
>> >ice cream sundae: It specifies a completely different plating layup:
>> >If no caps, the outer metal surface of all conductors and pads is
>> >plated at the same time the via walls are plated. This is a very
>> >good thing since it is easy to get plenty of "wrap" at the corner
>> >between the plated via and the surface metal. If you demand plated
>> >caps, then two separate plating cycles are needed. You may think
>> >that is no problem, but it creates a natural place to crack the via
>> >rim. This is why IPC specifies a minimum "wrap plate". This "wrap
>> >plate" is typically achieved by overplating a
>> "doughnut"
>> >around the via. That "doughnut" creates a bump on the top surface
>> >which creates problems for photoresist, imaging, and etching. To
>> >reduce the
>> bump,
>> >fabricators use some kind of abrasive process to thin it down to
>> >close to the IPC required minimum wrap plate. But that is a very
>> >difficult process to control, and I have seen large variations in
>> >"wrap plate" across a
>> panel.
>> >
>> >Since most customers of fabricators don't seem to have the capacity
>> >to understand the above, fabricators have responded by defaulting to
>> >plated caps if you request complete fill.
>> >
>> >Wayne Thayer
>> >
>> >On Thu, Aug 22, 2019 at 10:39 AM Dave Schaefer
>> ><[log in to unmask]>
>> wrote:
>> >
>> >> Jack,
>> >>
>> >> Save yourself some trouble and spec VII filled and capped.
>> >> Gives the added benefit of protecting from solder flow to opposite
>> >> side during manufacture and the process requires all vias to be
>> >> properly
>> filled.
>> >> My experience with other fill methods has never yielded acceptable
>> >> results: either ended up with about 10% of vias not fully filled
>> >> or with material seepage resulting in manufacturing issues due to
>> >> the impact on
>> the
>> >> paste application process.
>> >> Going from V to VII will cost slightly more (3-4% here) but that
>> >> is insignificant in comparison to the costs of failures of
>> >> assembled
>> product.
>> >>
>> >> Hth,
>> >> Dave
>> >>
>>
>> Thanks, but your post prompted another question:
>> (since you don't think Dave's reason is good enough)
>>
>> When are caps on filled vias required by an application?
>>
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