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May 2022

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Subject:
From:
R Saravanan <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, R Saravanan <[log in to unmask]>
Date:
Tue, 3 May 2022 09:04:24 -0500
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Hi,
We  are buying PCBs for Avionics applications . One of the acceptance test is 3 solder dip @288 Deg C.
We are observing laminate cracks in the C Stage of the Coupon in Thermal Zone. All the standards says laminates defects not to be evaluated in thermal Zone.

What caused the laminate cracks after thermal stress ? why is not evaluated in thermal zone ?

The PCB  is 3.2 mm thickness , 8 layer pcb.  

No laminate cracks are observed in as received condition and in reworked samples.

Interconnection of the stressed coupon is OK 

Can u clarify?

R.SARAVANAN

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