To minimize your risks it should be avoided. If you have to do it you
have to properly design your stencil to over come the solder drain.
There will be a noticeable difference between a VIP site and a non-VIP
site but you can get reliable solder joints that consistently meet IPC
requirements.
As I said earlier I would not recommend doing through VIP in less than
50 mil pitch SOIC, PLCC, SOJ's or discretes less than 0805. All old
technology. We used 13 mil drill which yielded typically a 10 mil
finished hole. We have done 8 mil FHS and put VIP in 0603's but you fab
cost goes up because you can't stack drill as many. Through VIP is
really becoming a dinosaur become you are limited to old technology.
Blind VIP is the new technology and that has issues as well.
The biggest risk is the PWB fab. Typically when we have had problems it
usually turns into a PWB issue. Usually we have found rough holes which
turn in to a plating issue. We have also had situations where the via
information was not properly transferred to the gerber data and the
stencil was not adjusted properly and we had to replace the stencil.
We try not to use VIP anymore but with our product lifecycle we still
numerous PCA's in production. Via filling for both through VIP and
Blind VIP is becoming the best alternative.
I apologize for my "whining" comment. I will clarify that to make money
EMS' want things as standard as possible. They do have to deal with a
lot of design issues that they have no control. In this case we built
these for years and I have had several EMS' that have worked with us and
built VIP products successfully for years. I have one that chooses to
whine about it yet cannot present evidence or data to support their
complaints. If they are having a problem one would think it would be
easy to generate the data. It is a specific EMS issue and not the
general statement that I made. Enough on my whining.
Russell Nowland
Alcatel-Lucent
Supply Base Engineer
Address: 14000 Quail Spring Parkway, Suite 300
Oklahoma City, OK 73134
email: [log in to unmask]
Desk: 405-302-1660
Cell: 405-203-0034
Fax: 405-302-1622
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of BADRI
Sent: Wednesday, February 28, 2007 1:04 AM
To: [log in to unmask]
Subject: Re: [TN] Via in Pad question
Hello,
Had a nightmare in this issue last week. The boards we were assembling
had
open vias in the pad. All the solder flowed thru the via to the bottom
side
leaving nil solder for the component. We had to go for a redesign of the
PCB. Try to avoid via on pad.
Thanx
Badri
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Carl VanWormer
Sent: Tuesday, February 27, 2007 10:28 PM
To: [log in to unmask]
Subject: [TN] Via in Pad question
I am looking for guidance on using vias in pads of surface mount
components. The concept is great for high speed design, since it gives
the least inductance for mounting bypass caps. It sounds easy, but I'm
sure there are some pitfalls and there may be some rules I will break.
Any guidance towards documents on this combination would be appreciated.
Also, any stories to scare me away from this approach will be fun to
hear.
Later,
Carl
Carl Van Wormer
Cipher Systems
1800 NW 169th Place, Suite B-100
Beaverton, OR 97006
Phone (503)-617-7447 extension 20
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