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Date: Fri, 17 May 1996 09:43:34 -0400
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From: Gary Ferrari <[log in to unmask]>
Subject: Re: Open vias problem
Cc: [log in to unmask] (IPC TechNet Forum), [log in to unmask]
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Mark;
You raise a number of issues:
1. What material are the boards made out of. I need more information than
just FR4. I need to know the exact type of material, eg. difunctional,
multifunctional, Tg, etc.
2. The IPC ran a small hole round robin testing program a little while back.
The results are in Technical Report IPC-TR-579. One of the results was
failure of high aspect ratio holes in the resin rich areas of a circuit
board. A 0.013 inch diamter via in your 0.093 inch thick board definately
falls into this category.
What I suspect is happening, is that the board material is expanding, in the
Z-axis, during your assembly process and cracking the via barrel. Use of a
higher Tg material will usually alleviate this condition.
3. Many small holes are being specified to plate shut. If the fabricator has
well controlled plating processes, then this is definately a good
"tolerance" to give him. However, if his process does not produce even
plating on the hole walls, of high aspect ratio holes, then you run the risk
of trapping plating solutions in the center of the hole structure. This
could potentially be a reliability problem.
4. If you are providing a CAD netlist to your vendor, then you should be
assured that his netlist electrical test is accurate. You must specify, in
your purchase order for a CAD netlist test. However, if you are only
providing gerber data, then he is suspect of incorrect electrical test
performance.
At 04:11 AM 5/17/96 CDT, [log in to unmask] wrote:
>Hello,
>
>We assemble circuit boards in a high product mix/low volume environment.
>I'm uncomfortable about some PWB defects that were detected by our ATE
>test equipment recently (i.e. testing of fully assembled/soldered circuit
>board assemblies). "Open" vias were detected in a few instances. In
>other words, there wasn't continuity between the top side and bottom side
>pads for the via.
>
>For one particular part number we had 3 boards with an open via on each
>out of 94 boards total. The previous month we had 1 board out of 114
>exhibit this problem. This board is a .093" thick 4-layer SMOBC surface
>mount board.
>
>Another part number we experienced this problem with had an open via on
>each of 3 out of 210 boards total. This board is a .062" thick 6-layer
>SMOBC surface mount board.
>
>In both cases, the vias are specified to have a finished diameter of
>0.013". However, in both cases we've allowed them a minimum diameter
>of 0 per their request (i.e. we won't reject any for vias plated shut).
>
>Both of these part numbers are supposed to be 100% electrically tested
>by the PWB supplier with a clamshell tester. Therefore, ideally, I
>would've expected zero instances of this type of problem.
>
>QUESTIONS...
>
>Is there anything wrong with allowing vias to plate shut?
>
>Which PWB fabrication process(es) would cause an occasional open via?
>
>Isn't it fair for me to expect their electrical test to detect these?
>
>Should I be concerned about the via integrity in every board supplied
>by this PWB fabricator, regardless of whether it passed our ATE test
>or not? (i.e. is this a sign of something far worse)
>
>How would you proceed in this situation?
>
>Please e-mail responses to [log in to unmask] Thanks - any assistance
>is appreciated.
>
>Regards,
>
>Mark Lettang
>
>
Regards,
Gary Ferrari
Chairman IPC-D-275
Tech Circuits
(203)269-3311
[log in to unmask]
======== Fwd by: Tony King / N ========
A standard via tolerance requested by the board fabricator would be +0.003"
-the hole diameter. It should not be assumed that the hole is plated shut
though, the odds of this are minimal. The holes would be more likely plugged
with solder at hot air solder level, however if the tolerance was +/-0.003
on the via, a solder filled via would be cause for rejection.
I agree with the above statement that if a net list is not supplied, the
fabricator has no option but to extract a net list from the raw data and
test to that net list. If the customer supplied data was incorrect, the
product would be built as such. The fabricator has no way to determine
otherwise.
Boards are often designed with one side of a via plugged after HAL to allow
vacuum draw at in circuit test, while leaving the other side of the via open
as a test point. The board fabricator uses a CAET software which detects
plugged via conditions and since mask is over that side will omit them from
the test program. In this test example, the entire via hole could not be
tested top to bottom unless the path of the net went top to bottom on of the
hole (ie: double sided surface mount)
Voids can occur as a result of thermal stress, the highest aspect ratio
holes would plate less in the middle. More often though, void in via holes
is a result of electroless copper not coating the entire hole barrel. A
small via tends to hold air bubbles and prevent chemistry from flowing
through. The problem is exagerated by poor drill quality, gouging and
debris. A void of this kind would be ring shaped, circumferential and could
be identified by micro section analysis. I do not believe this type of void
should cause doubt in integrity of all other product.
Tony King
Elexsys International
603-886-0066
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