In a message dated 8/20/99 3:11:33 PM Central Daylight Time, [log in to unmask]
writes:

> I am looking for a rule of thumb regarding the maximum ramp standard
>  components (chip capacitors) can tolerate without failure during the reflow
>  process.  The standard seems to be 3C\second, but this figure is generally
>  derived from the average ramp rate a product experiences during reflow.
>  Ex: A very light board spends 60 seconds in the first zone of a short
>  convection oven, which is set to 150C, and is at 150C at the end of that
>  zone. (Assume 30C ambient for simplicity)  The averaged ramp rate for the
>  zone would be 2C\sec--an acceptable profile statistic .  But what is
>  actually happening is the board is reaching 150C in the first 20 seconds of
>  the profile, which gives an actual ramp rate of 6C\sec--well over any
>  established rule of thumb.
>  My question is: What is the ACTUAL ramprate, in Degrees C\second (and
>  duration at degrees\second), that chip capacitors can stand without
>  cracking, etc...
>
>  Thanks,
>  Greg Jones

Hey Dr. J!

(cool screen name by the way) anyhoo, go to:
http://www.avxcorp.com/tech/techpdf/smzero.pdf and it'll be a splat dot PDF
file that comes from an obscure capacitor manufacturer that details out the
process requirements for zero-defects (ha,ha,ha...) I shouldn't be so
pessimistic, should I? Sorry 'bout that...anyways, it's their
recommendations....

-Steve Gregory-

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