If you give them a minimum diameter of 0, then how do you know they 
     drilled it and then plated it vs. not drilling and just plating the 
     pads?
     
     We had recent problems with drill data (due to our error in our 
     aperture file).  We could not detect the problem until PCB test 
     because we used the same data to check by as what we used to make the 
     PCB!  If the vendor made the board to the wrong data, chances are that 
     his electrical test fixture will be just as wrong (i.e. verifying the 
     error was put in accurately).
     
     Regards,
     
     Roger Held
     Hitachi Computer Products (America), Inc.


______________________________ Reply Separator _________________________________
Subject: Open vias problem
Author:  [log in to unmask] at Internet-HICAM-OK
Date:    5/17/96 4:11 AM


Hello,
     
We assemble circuit boards in a high product mix/low volume environment. 
I'm uncomfortable about some PWB defects that were detected by our ATE 
test equipment recently (i.e. testing of fully assembled/soldered circuit 
board assemblies).  "Open" vias were detected in a few instances.  In 
other words, there wasn't continuity between the top side and bottom side 
pads for the via.
     
For one particular part number we had 3 boards with an open via on each 
out of 94 boards total.  The previous month we had 1 board out of 114 
exhibit this problem.  This board is a .093" thick 4-layer SMOBC surface 
mount board.
     
Another part number we experienced this problem with had an open via on 
each of 3 out of 210 boards total.  This board is a .062" thick 6-layer 
SMOBC surface mount board.
     
In both cases, the vias are specified to have a finished diameter of 
0.013".  However, in both cases we've allowed them a minimum diameter 
of 0 per their request (i.e. we won't reject any for vias plated shut).
     
Both of these part numbers are supposed to be 100% electrically tested 
by the PWB supplier with a clamshell tester.  Therefore, ideally, I 
would've expected zero instances of this type of problem.
     
QUESTIONS...
     
Is there anything wrong with allowing vias to plate shut?
     
Which PWB fabrication process(es) would cause an occasional open via?
     
Isn't it fair for me to expect their electrical test to detect these?
     
Should I be concerned about the via integrity in every board supplied 
by this PWB fabricator, regardless of whether it passed our ATE test 
or not?  (i.e. is this a sign of something far worse)
     
How would you proceed in this situation?
     
Please e-mail responses to [log in to unmask]  Thanks - any assistance 
is appreciated.
     
Regards,
     
Mark Lettang