I am not sure what "Standard Test Point Coverage" means, but I can tell you
that using the term "100% Electrical Test" as a specification to vendors
leaves great chances for escapes. The problem is the term "100% Electrical
Test". It has no definition. There are many issues involved in keeping
escape rates low. The following is a list of items that should be specified
to a bare board manufacturer for electrical test. It is far from complete,
but these are some of the key items.
Fixturing Method - a board tested in a single pass on the test system will
have a lower rate of escapes than one that is tested in multiple passes.
Methods like "flip testing", "split net testing", and "combinational
testing" are test methods used when the test features are so densely located
or so fine and small that they can not be easily accessed. The necessity
for these compromised test methods is highly dependent on the vendors
equipment. These methods are often used to extend the life of older or
obsolete equipment and fixturing styles.
Test Point Optimization - don't optimize unless test point density requires
it to test the board in a single pass. Optimization algorithms are not
perfect. There are so many different design methods and designers that the
algorithms inevitably remove some points from the test that shouldn't have
been. Don't risk it if you don't have to.
Test Parameters - there are 4 major ones (Voltage, Current, Isolation
Resistance, Continuity Resistance).
Voltage - is the least critical. IPC-ET-652 states it best as high enough
to provide sufficient current for the measurement in question, but low
enough to prevent arc-over. 100 Volts is the most common.
Isolation - 100 MegOhms is the most stringent and can be challenging for the
vendor, 10 MegOhms is a very good test.
Continuity - 10 Ohms is very stringent and will only be achievable by the
higher end vendors with modern equipment
Current - you want as little as possible, high currents can actually create
faults/escapes. 10 mOhms is a good tight spec..
Board Marking - automatic, eliminate the human error here. Further if your
assembly equipment can look for the mark it can avoid loading boards that
were stacked in correctly or not tested.
In process resolution of discrepancies is the last item I'll mention. There
should be a means for the vendor to quickly contact an appropriate
individual to ask if it is ok to do such and such. There are often data
issues that when assumptions are made lead to problems and escapes. These
contacts can lead to less compromises in test, quicker turn and cost
savings.
There is a chapter in the Printed Circuits Handbook, 4th edition (1996)
devoted to Bare Board Electrical Testing. The book is available from
McGraw-Hill.
I would be happy to discuss this or any topic related to bare board ET
further. I can be reached directly at (617)942-7030 or
[log in to unmask] Good luck.
----------
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Subject: Re: Test Point Coverage
Date: Friday, March 29, 1996 11:35AM
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Response to:
=================================================================
Is there a Standard amount of Test Point Coverage at the PCB Bare
Board Supplier during Electrical Test in which an NRE setup and
100% Electrical Test of PCB's was charged.
What is the chance of Escape associated with Electrical Test?
Thanks in advance for any help given.
[log in to unmask]
=================================================================
Nancy those are good questions.
I would like to see all the responses to your questions. Although
I have been in the bare board manufacturing the and PCB design
business for more that 25 years I can't answer your specific
questions. The following is just my engineering opinions.
First and formost is you get what you specifically ask for and
you pay for all of it.
If you specifically ask for electrical testing of a Bare PCB, you
should contact the supplier to understand the limitations of their
board board tester prior to designing your PCB and understand the
coverage vs cost for various guaranteed reliability levels of product.
Assume that you want to test 100% of all unique printed circuit
features on one finished bare PCB for all possible shorts and opens
conditions. Certainly you want each bare board to pass this test.
You must design the PCB such that the Bare board tester can reliably
contact ALL ends of All discrete printed circuit voltage, ground and
signal nets simultaneously. This can be costly and would limit your
design density to the tester probe to probe minimum grid and maximum
number of probes allowed by the test equipment. Any design that
does not allow for this complete coverage leaves some % posibility of
defect detection escapes. The answer is one of statistics for the
specific board design in question. Each net has the risk of shorts and
/ or opens along it's entire path. Which other nets it has a risk to
short with is a function of the routing path that that specific net
takes. The amount of risk is a function of the length and spacing of
each net to the other. Net to net shorts risk sites go up as the
length that nets run adjacent to each other on any metal plane level
in the bare board increases. You can see that the % of coverage
and % of potential escapes is very dependant on the specific test and
tester that the bare board fabricator uses. As the PCB is designed
with thiner printed circuit lines the risk of pc net opens goes up.
As the PCB is designed with closer line to line spacings the risk of
pc shorts goes up.
Manufacturing test engineers for bare board products need to calculate
the % coverage and % defect escapes vs the risk and cost factors for their
business. NRE will be charged for any unique software or hardware that
is needed for testing your bare board. The rest of the cost for testing
should be buried in the unit cost of the bare board.
I know that I did not answer any of your specific questions but as I
suggested, contact each bare board manufacturer to get the specifics
on their definition of "100% Electrical Test".
100% electrical test might mean 100% of all possible shorts and opens
were tested for on some statistically significant sample size of
each lot of PCBs produced and shipped. The remainder of the PCBs in
the lot might have had optical inspection only.
Bare board testing for net to net shorts is sometimes done at the assembler
prior to component attachment processes but this would add cost that you
(the customer) would like to eliminate.
The major assumption you have to make with all bare board testing is
that your bare board manufacturer has qualified their processes and
product to be reliable after stress testing. Stress testing must
simulate the subsequent manufacturing and functional usage conditions
that the bare board is subjected to in it's product life. Bare boards
are not stress tested as part of the normal manufacturing process.
If you don't specify the type and extent of testing you want on a PCB
you will get only what the PCB manufacturer can afford and still be
competitive in their industry. Sorry if this is no help to you, but
who said that electronic packaging engineering is simple.
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