Kim

IPC-HDK-001 does mention stacking / piggyback of chip components for
prototypes or small lot runs.
For ICs, one of  concern will be thermal disssipation.The Piggyback is
difficult to automate.  e.g.I remember a case for stacking SOIC 20s . We
reflow soldered bottom IC , applied glue on top of IC and glued second
IC and oven cured. All that was run on SMT Assembly Line. Fun part
started from here onwards. The Individual leads were manually soldered
using Jumper Tracks. That meant lot of work. Again, it was customer
approved due to component obsolence problem.


Ashok Dhawan P.Eng
Engineering
C-Mac Electronic Systems Inc.
1455 Mountain Avenue
Winnipeg, Manitoba R2X 2Y9
Canada
Phone: (204) 631-7208
Fax: (204) 631-7294
E-mail: [log in to unmask]
www.cmac.com

 >>

All,

I have been searching for information regarding the stacking of
components,
(all types) on pcb assemblies. I have yet to find any IPC standards with

any
such information as to what is acceptable and not. Mainly all I hear is
if
it is documented on the process, and the solder workmanship meets all
IPC
criteria, then it's acceptable.

Any thoughts or suggestions as to where I could maybe find more
information
regarding such practices? I see alot of cutting of traces, and kluge
components to any thing that will solder, jumper wires, etc.

Kim Anderson
Internal Quality Auditor
IFR Americas
316-522-4981 X-479