people,
forwarding some mail regarding all the discussion on decoupling caps.
This is from an e-mail about general emi issues on a regulatory
newsgroup. However it is mostly about decoupling.
Use at your onw risk!
joez
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Joseph Zdybowicz FORE Systems
CAD Engineer 174 Thorn Hill Road
Email: [log in to unmask] Warrendale, PA 15086-7586
Direct: 412-772-6552
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> Decoupling & Stackup
> ---------------------------------
>
> The basic concept involves minimizing the inductance and loop area of
> the charge path from the power supply to the load. For this discussion,
> the power supply can be considered the closest charge storage device
> (decoupling capacitance) to the load and the load can be considered all
> of the simultaneously switching devices within the die of an IC near the
> power
> supply.
>
> On-Chip Decoupling
>
> It is not trivial to actually design a power supply system that meets the
> needs of transient events asking for current at 300 MHz+. Even with really
> good
> mother board "distributed capacitance," there is inductance through the
> leads
> within the IC packages. This can be mitigated by using a huge number of
> power and ground pin pairs on the chip since these inductances parallel.
> However, we are now talking about switching events in processors
> producing significant low order harmonic content of 1 GHz+.
>
> These days, it is prudent to design in as much capacitance
> between VCC/gnd within a large IC as possible, so that there is some
> charge available at 1+ GHz for the 4th or 5th harmonic of the IC clock
> (often an ASIC PLL) through as small a loop inductance and loop area
> as possible. Therefore, decoupling should be implemented at the IC
> package/die level on high frequency devices (100 MHz and up). The
> board designer has little control over this unless involved at the chip
> design level.
>
> Board Distributed Capacitance Decoupling
>
> Good board distributed capacitance requires adjacent stacking of VCC
> and ground layers with thin dielectric , <4 or 5 mils, and high dielectric
> constant.
> The capacitor is the two layer structure and dielectric in between; there
> is essentially no inductance between the layers.
>
> This helps to reduce VCC/ground bounce at frequencies of 300+ MHz
> to manageable levels on the motherboard. Multiple VCC/ground structures
> as described above with perimeter via stitching of the ground layers (0.1"
> to 0.25" apart between vias) further reduces plane inductance and perhaps
> field fringing at the perimeter of the motherboard. With at
> least two VCC/gnd layers and an 8 layer board, you can now bury
> clocks in the two board center layers and maintain a symmetrical stackup
> with good board distributed capacitance.
>
> The layer count grows further as you need to consider multiple DC voltage
> supplies and dense signal routes. This trend has been getting much
> worse as of late with +3.3V and 5V supplies, regulated and unregulated,
> filtered and unfiltered. 12 to 14 layers is optimal for complex
> designs.
>
> I've done one 50 MHz bus clock motherboard board in 6 layers
> without adjacent VCC and ground layers (it was a mandate of the project)
> and the bus clock noise put quite an EMI load on the mechanicals for
> Class B. It would have been worth paying more for the extra layers since
> I could have pulled cost from the chassis, but it was a tough sell
> politically
> with the product bosses.
>
> Excessive ground bounce has obvious implications for both
> box and cable radiation. Again, if too few layers are chosen for a high
> frequency
> layout, the savings in board cost can easily be chewed up in shielding,
> gasketing, and ferrites.
>
> Discrete Board Decoupling Caps
>
> As far a board discrete decoupling goes, I consider these useful
> below 300 MHz, the first harmonic of some processor clocks and
> the 4th or 5th harmonics of memory/system bus clocks. Since this
> is where the majority of current is produced, there needs to be
> plenty of larger discretes (0.1uF/1000pF) and plenty of bulk
> behind them. these devices are just too inductive and too slow
> to supply charge at frequencies above 200 MHz to 300 MHz.
>
> Ground Referencing
> ------------------------------
>
> Also, I am now of the opinion that
> the board logic grounds should be DC coupled to the chassis metal at as
> many AREAS of contact as is possible. This takes advantage of all of
> the capacitance of that big chunk of chassis metal that we pay for; it
> further reduces ground bounce. HOWEVER, IT IS ABSOLUTELY ESSENTIAL
> THAT ALL METAL CHASSIS PANELS BE WELL REFERENCED TO
> THE MAIN CHASSIS through low inductance paths, or one may set up
> efficient dipole structures between panels that can be excited by a noise
> source.
> I have also done designs where logic and chassis ground are separated at
> the I/O and this does seem work if it is done right (the 6 layer 50 MHz bus
> clock
> motherboard used this design method while our newer high speed designs use
> the DC-coupled logic ground approach). I just don't think separate logic
> and
> chassis ground approach fully takes advantage of the chassis capacitance,
> which represents a "stiffer" AC reference.
>
> Dielectrics
> ----------------
>
> Concerning dielectric constants, it is my understanding that at 50+
> Mhz, these "constants" actually can vary with frequency (considerably
> above 1 GHz). This would suggest that as frequencies get higher,
> the actual board dielectric chosen can be the source of tuned transmission
> line impedance variations, clock skew, timing errors, and perhaps higher
> emissions
> from the board. I don't have much experience in the area of dielectrics
> and would like to hear if anyone knows of a good, CLEAR written treatment
> of this topic.
>
>
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