Mail*Link(r) SMTP               FWD>FAB: Edge Plating

Ted --

You're right, I don't know of any and we couldn't find any requirements for
"edge plating" of the periphery of printed boards or cut-outs in printed
boards out there either.

>Date: 5/16/96 10:50 AM
>From: Edwards, Ted A (AZ75)
>[log in to unmask]

>We procure microwave boards that to IPC-HF-318 would be Class 3 Type 3. 
>Recently we see some suppliers having problems which result in plating 
>voids.  The criteria for voids in a plated through hole are defined but 
>voids in the plated edges of the board do not seem to be defined anywhere.

So what we did was to include the requirements in notes on the product
definiton (master) drawing.  We specify the plating thickness shall meet the
plated-through hole thickness requirements. Depending on the design
requirements, we allow edge-plated voids to be a percentage of printed board
thickness, or more generally, one board thickness in size (length and width). 
At first we specified an adhesion requirement using the ol' tape peel test, it
worked for epoxy and polyimide base materials, but not for thicker PTFE base
materials. Blisters / unbonded areas are not allowed for Class 3 because it is
unknown if the  separated area will propagate due to volatile materials in the
base material or separation.  For Class 2, the edge blister / separation can
be up to two base material thicknesses long for most operating environments. 
Most of the requirements are based on the responsible design engineer's (not
the printed board designer or manufacturing) assessment (based on testing /
knowledge / experience) for that particular (or similar) design.

>    Question 1. A void across an interconnect in a normal multilayer is 
>                real bad but what about a void across the same interconnect
>                when it is a ground that goes all the way around the
periphery
>                of the finished board?

A "peripheral void", or even a small percentage of the periphery of the
perimeter of the printed board or a cutout is a no-no.  Care must be exercised
to ensure the "peripheral-like" voids are a small percentage of the wavelength
of the highest frequency of concern (that's why we decided to limit voids to
generally one board thickness).  Voids should not be allowed to occur in a
linear pattern of approximately uniform pitch.  The concern is the 0.5
wavelength effects of the spaces (voids) between ground connections at the
highest operating frequency.  

>    Question 2. Does anybody know where plated edge requirements are
>                listed?

Nope, we adapted tradition plated-through hole requirements as mentioned
above.

>    Question 3. Since I can not find what I am looking for in a 
>                specification, if no specification exists, does anybody have
>    >                criteria?

Included above.

Hope this helps,
Ralph Hersey
e-mail:  [log in to unmask]

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Date: 16 May 1996 12:05:11 -0500
From: "Edwards, Ted A (AZ75)" <[log in to unmask]>
To: "[log in to unmask]" <[log in to unmask]> (Return requested)
Subject: FAB: Edge Plating
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