Randy,
In reference to the 60% resin filled hole in buried vias in IPC-RB-276. The
hole fill data came from a couple of large users who had tested this number
and had found it to be acceptable to the thermal shock and thermal stress
testing.  There was no tests data to support completeley unfilled buried vias
so it was only allowed in Class  1. 

The information was based on the process for late 1980s which usually
employed only one internal layer about 6 mils thick with a 8-10 mil diameter
hole, aspect ratios were never greater than 2.  Today, we put a 6-8 mil hole
in a a 6 to 10 internal layer with aspect ratios greater than 6.  However, I
have not heard of any problems with the partially filled buried via holes.
 With the completely filled hole I have heard that when blind vias were made
by the buried via technique and overplated on the surface, the high CTE
unfilled resin plug in the hole expanded during soldering and cracked the
barrel of the hole near the surface.  Another report about the same technique
indicated that a bump appeared on the SMT land and made mounting difficult.

If anyone has any data on high aspect ratio buried via holes that are resin
filled and partially resin filled, I would appreciate it for inclusion in the
in-process performance IPC-6012.

Phil Hinton 
Hinton "PWB" Engineering 
[log in to unmask]