1) This is a factor of the via size. We flash an initial deposit on the via cap, then this is over plated with a nominal ~ .0012" plating thickness. Larger via diameters have an increased propensity for adhesion loss and we target a thicker flash and final deposit.
2) Non-conductive via fills should be materials designed for this purpose - high filler content, stable CTE and low shrinkage coefficient. Using an LPI or standard epoxy fill may lead to issues, including the one discussed in item 1.
3) For PCB - standard 288C float(s) for 10 seconds should present and issues that maybe experienced during assembly and duty cycle. An initial qualification testing should be performed with thermal shock testing. If done correctly, the via-in-pad design in invisible to the assembly operation/performance.
Jeffrey Bush
Director, Quality Assurance and Technical Support
VERMONT CIRCUITS INCORPORATED
76 Technology Drive - POB 1890
Brattleboro, Vermont 05302
Voice: 802.257.4571.21 Fax: 802.257.0011
http://www.vtcircuits.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Linda.Li
Sent: Tuesday, October 25, 2005 10:57 PM
To: [log in to unmask]
Subject: Re: [TN] SV: [TN] Via in pad finished flatness-3 more questions
Hello all,
Good day!
I am new to the Technet, I am very glad to join this team when I see so many PCB experts here whom I can learn from.
I want to take this chance to ask 3 more questions about via in pad design.
1) What's the minimum plated copper thickness over the via? I have heard that if the copper is too thin, it will be easily peeled off during assembly. Is this true?
2) Do you have any special requirement for the non conductive fill ink? What factors will you consider when you choose the fill ink?
3) What kinds of reliability tests should be done for the via in pad design except for thermal cycle test? Or do you have any concern about reliability of the via in pad?
Thank you very much in advance!
Best regards,
Linda Li
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Ingemar Hernefjord
Sent: Wednesday, October 26, 2005 4:21 AM
To: [log in to unmask]
Subject: [TN] SV: [TN] Via in pad finished flatness
Our spec says maximum Ra = 3 micrometers
Ingemar Hernefjord
Ericsson Microwave Systems
-----Ursprungligt meddelande-----
Från: TechNet [mailto:[log in to unmask]] För David Greig
Skickat: den 25 oktober 2005 16:02
Till: [log in to unmask]
Ämne: [TN] Via in pad finished flatness
Hi TN,
>From an assembly perspective, what is the maximum surface roughness
tolerable for via in pad 0.5mm pitch BGA, particularly
larger parts with pin counts >=80?
Same topic, but from a fabrication viewpoint:- What is achievable using
either 1 stage plated shut process or a 2 step process
using filled/levelled microvia which is then plated over?
Best Regards
David Greig
______________________________
GigaDyne Ltd
http://www.gigadyne.co.uk <http://www.gigadyne.co.uk/>
<http://www.gigadyne.co.uk/>
______________________________
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