TECHNET Archives

August 2019

TechNet@IPC.ORG

Options: Use Monospaced Font
Show Text Part by Default
Show All Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
Subject:
From:
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, [log in to unmask]
Date:
Fri, 23 Aug 2019 11:28:52 +0000
Content-Type:
text/plain
Parts/Attachments:
text/plain (19 lines)
Fellow TechNetters:

   I did not receive any feedback on my first inquiry.   Therefore, I submit my request below again.

Victor,

From: Hernandez, Victor G
Sent: Thursday, August 22, 2019 10:14 AM
To: TechNet E-Mail Forum
Cc: Hernandez, Victor G
Subject: IPC-TM-650 - 2.6.8, 06/04 Rev: E, D-33a, Thermal stress, Plated Through Holes

Fellow TechNetters:

   Is it valid/acceptable/permissible/allowable to conduct the above stated Test Method on a raw board with a final surface finish of LF HASL?
All comments and suggestion welcomed.....

Victor,

ATOM RSS1 RSS2