I have a question about the solderabilty requirements on chip resistor
and capacitors per J-STD-001D. I have solder wetting up to the top of
chip components where in come cases there is a distinct line of
demarkation. In other cases the solder wets over the end termination of
the part and has a smooth wetting angle. Is a visible line of
demarkation rejectable per J-STD-001 soldering requirements (para 4.14).
The requirment is for a 50 percent solder fillet height and although a
smooth wetting angle is perferred - is a line of demarkation (non
wetting vs dewetting) a cause for rejection? I am using 63/37 eutectic
solder so the alloy is not exotic.
Thanks much
Tom Gervascio
Senior Process Engineer
Sypris Electronics
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