In your message dated Wednesday 23, October 1996 you wrote :  
>      I recently attended the University of Wisconsin's "System EMC 
>      Compliance through Printed Circuit Design" seminar and was taught that 
>      if the external planes are for shielding purposes, it is a good idea 
>      to run a guard ring of ground around the periphery of the board on all 
>      layers and tie the external planes and the internal ground plane 
>      together through closely spaced (.25 inch) vias only at the guard 
>      ring. Tying the IC and Cap ground pins to the external plane only puts 
>      noise onto the shield.  The course contained other subtle tricks. Take 
>      it if you can get the chance.
>
There are serious cost implications here with a significant increase in hole 
count together with reduced stack height for small holes. This could up the 
drilling cost by a factor of 3 or more. On one design we had to manufacture, it 
added 5000 holes to the panel.

I was also wondering what the impedance characteristics would be like for 
inner layer signal tracks running close to the vias. Would it be spiky with the 
fluctuating dielectric? Does it matter?

If there is no other way of shielding within the casing of the finished unit, 
then perhaps edge plating could be a lower cost method and certainly more 
uniform. This would mean routing the profile, leaving attachment points, at the 
first drilling stage. The attachment points are then routed through at the final 
profile stage. If the screening is really critical, vias could be placed at the 
points where there will be no plating.

We have done this on a number of designs over the years with no manufacturing 
problems.
-- 
Paul Gould
Teknacron Circuits Ltd
EMail [log in to unmask]

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