>
>Re fine lines on PWB's:
>
>I'd like to see a discussion on why it is so difficult to make "fine line"
traces on PWBs .... My background is first level where two mil lines are
standard and line widths and spaces of 0.0005/0.001 are achievable in 80K A
copper (about 0.0003"). Is the problem with the resist technology, the
expose capability, or the etcher? Or somewhere else?
>
>Why not go to thinner copper (i.e. 0.0005")? For CMOS logic, the resistance
should not be a factor. 
>
>What about switching to additive? I know IBM does 3 mil lines with additive
in high production on very large panels, albeit on high end (probably
expensive) boards. Is this technology not transferable to low cost? 
>
>My perception is the IPC "roadmap" will not meet the requirements of the
advanced system designers ... things take too long to get done. What would
it take to make fine line PWBs standard and cheap??
>
>
Ron Gedney
[log in to unmask]
Integrated Electronic Eng. Center
Watson School of Eng. & Applied Science
Binghamton University
P.O. Box 6000
Binghamton, NY 13902
607-777-4335, fax 4683

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