Greg;

  I will confuse you with another question :
  Why worry about ramp rate during reflow if bottom side ceramic capacitors
has a ramp rate of 100 to 150C/sec during wave solder ???? ( This happens
when they exit from pre heating and touch the molten solder during few
seconds )

  I believe who that could explain this too has the right answer ...

Thanks


> -----Original Message-----
> From: Greg Jones [SMTP:[log in to unmask]]
> Sent: 20 de Agosto de 1999 17:08
> To:   [log in to unmask]
> Subject:      [TN] Thermal stress in reflow
>
> I am looking for a rule of thumb regarding the maximum ramp standard
> components (chip capacitors) can tolerate without failure during the
> reflow
> process.  The standard seems to be 3C\second, but this figure is generally
> derived from the average ramp rate a product experiences during reflow.
> Ex: A very light board spends 60 seconds in the first zone of a short
> convection oven, which is set to 150C, and is at 150C at the end of that
> zone. (Assume 30C ambient for simplicity)  The averaged ramp rate for the
> zone would be 2C\sec--an acceptable profile statistic .  But what is
> actually happening is the board is reaching 150C in the first 20 seconds
> of
> the profile, which gives an actual ramp rate of 6C\sec--well over any
> established rule of thumb.
> My question is: What is the ACTUAL ramprate, in Degrees C\second (and
> duration at degrees\second), that chip capacitors can stand without
> cracking, etc...
>
> Thanks,
> Greg Jones
>
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