to be fair, I wish I could lay claim to coining the term thermal via farms.
To be fair I think I first heard it whilst sipping a very dark bitter adult
beverage somewhere in Arizona with one of the Merix crew at a Rogers
Wireless Workshop. Methinks twas Doug Trobaugh or maybe Mike McMaster or
Gary Pollard.
cheers,
dw
At 12:13 PM 10/19/2005, Whittaker, Dewey (AZ75) wrote:
>So if you did this right you would be a good farmer. Great, I always
>wanted to be known as a man outstanding in his field.
>Dewey
>
>-----Original Message-----
>From: TechNet [mailto:[log in to unmask]] On Behalf Of Karl Sauter
>Sent: Wednesday, October 19, 2005 12:07 PM
>To: [log in to unmask]
>Subject: Re: [TN] Delamination at Thermal Via area?
>
>Dwight,
>
>In many of our applications the copper plating over the via fill (fill
>material is NOT conductive) is needed to create a solderable pad for the
>solder joint forming above it that connects to a BGA device, or for good
>electrical contact to a socket. Therefore new assembly techniques may
>be needed to prevent excessive underlying laminate material heating
>rates as described in thermal via farm areas (good description).
>
>Regards,
>Karl Sauter, Sun Microsystems
>
>
>Dwight Mattix wrote:
> > At 08:47 AM 10/19/2005, Karl Sauter wrote:
> >
> >> Dwight,
> >>
> >> How is heat to get from the device to the thermal via if you don't
> >> plate over it?
> >
> >
> > The via is plated, yes?
> > The via is connected to the surface copper at the knee of the hole,
>yes?
> > The thermal path is down through the knee of the hole into the via,
>yes?
> > Any plating over the via fill is a small to insignificant part of the
> > total % surface copper and therefore a small part of the thermal path
> > into the via, no?
> >
> > Been there, done that, got the T-shirt. It works.
> >
> > (warning Will Robinson) When using thermal via farms, you may find any
>
> > solution is so effective at conducting heat into the pwb that without
> > a thoroughly dried pwb, and a carefully controlled preheat/ramp the
> > pwb will be sensitive/prone to delam in those areas anyway. The risk
> > is accentuated when there's a high % of gnd fill on inner layers in
> > the area. These via farms w/ gnd fill is really good at passing heat
> > into the pwb fast and creating an unintentional thermal shock effect.
> >
> > The delam risk is ESPECIALLY high in this type via cluster when uVia
> > buildup layers are needed. Of course the uVia probably means use of
> > single ply dielectrics over buried via subassemblies. In those cases
> > the plating thickness on the sub needs to be minimized (more is
> > definitely not better), the buried vias need to be prefilled w/ resin
> > to prevent local resin starvation in the single ply layers.
> > Otherwise, the single ply will have to stick to tall copper and do it
> > w/out all the necessary resin (avoid 106 in this case and use at least
>a 1080).
> >
> > that's $.04 from me today. Still free and worth every penny. :^)
> >
> > cheers,
> > dw
> >
> >
> >
> >
> >> Agree that CTE of the non-conductive fill must be a very close
>match.
> >>
> >> Regards,
> >> Karl Sauter, Sun Microsystems
> >>
> >>
> >> Dwight Mattix wrote:
> >>
> >>> We have a lot of experience w/ this type failure. I'm working on
> >>> the assumption that there's a thermal via farm in that center gnd
>slug area.
> >>> A couple recommendations ff the cuff...
> >>> * Stay away from conductive via fill material whenever possible
>when
> >>> vias are tightly packed in "thermal via farms." Conductive fill is
> >>> almost
> >>> never needed -- adds very little actual thermal/conductive benefit.
> >>> We've
> >>> modeled it and test it. For my money, conductive fill is almost
> >>> always a waste of time and a real pain in the patootie from
> >>> reliability standpoint.
> >>> The biggest benefit is that it's easier to plate over and get good
> >>> copper adhesion and that usually only matters on probe sites. Esp
> >>> evil/unpredictable in this application is CB100 (I've had lots of
> >>> dialogue w/ Dupont over the years on this type failure).
> >>> * Use a non-conductive fill that's more closely matched in CTE
> >>> (e.g.San
> >>> eh) and don't overplate the fill.
> >>> * Arguably the most significant factor: don't plate over the
> >>> thermal vias. All overplating does is give the fill something to
> >>> push against and force the whole plated area up during thermal
> >>> excursions. It's like screwing a cylinder head on tightly and then
> >>> pushing all the pistons up against it (expanding fill at temp). Pop
>
> >>> goes the weasel! Overplating doesn't add any grounding or thermal
> >>> benefit. The solder joint in the gnd slug will still be fine w/ the
> >>> dot pattern that emerges.
> >>> * As a work around/mod: We've eliminated a couple of these
> >>> problems on finished product by just etching or laser ablating a dot
>
> >>> of copper off over the fill.
> >>> there's my $.02. Free and worth every penny. ;^) cheers, dw At
> >>> 07:29 AM 10/19/2005, Steve Gregory wrote:
> >>>
> >>>> Hi Wee Mei!
> >>>>
> >>>> I've got your pictures posted. Go to:
> >>>>
> >>>> http://www.stevezeva.homestead.com/files/U2_top.JPG
> >>>> http://www.stevezeva.homestead.com/files/U2_bottom.JPG
> >>>> http://www.stevezeva.homestead.com/files/U2_delamination.JPG
> >>>>
> >>>> Are the vias filled? Are you seeing this delamination on very many
> >>>> PCB's? Are you seeing it only on the bottom of the PCB?
> >>>>
> >>>> Kind regards,
> >>>>
> >>>> -Steve Gregory-
> >>>> Senior Process Engineer
> >>>> LaBarge Incorporated
> >>>> Tulsa, Oklahoma
> >>>> (918) 459-2285
> >>>> (918) 459-2350 FAX
> >>>>
> >>>>
> >>>>
> >>>> |---------+---------------------------->
> >>>> | | Wee Mei |
> >>>> | | <[log in to unmask]
> >>>> | | SG> |
> >>>> | | Sent by: TechNet |
> >>>> | | <[log in to unmask]>|
> >>>> | | |
> >>>> | | |
> >>>> | | 10/19/2005 03:47 |
> >>>> | | AM |
> >>>> | | Please respond to|
> >>>> | | TechNet E-Mail |
> >>>> | | Forum |
> >>>> | | <[log in to unmask]>|
> >>>> | | ; Please respond |
> >>>> | | to Wee Mei |
> >>>> | | <[log in to unmask]
> >>>> | | SG> |
> >>>> | | |
> >>>> |---------+---------------------------->
> >>>>
> >>>>
> >>>>
> >>>> >------------------------------------------------------------------
> >>>> --------------------------------------------|
> >>>>
> >>>>
> >>>> |
> >>>> |
> >>>> | To: [log in to unmask]@SMTP@Exchange
> >>>> |
> >>>> | cc: (bcc: Stephen R
> >>>> Gregory/LABARGE)
> >>>>
> >>>> |
> >>>> | Subject: [TN] Delamination at Thermal Via
> >>>> area? |
> >>>>
> >>>>
> >>>>
> >>>> >------------------------------------------------------------------
> >>>> --------------------------------------------|
> >>>>
> >>>>
> >>>>
> >>>>
> >>>>
> >>>> Hello,
> >>>>
> >>>> Just asked Steve to download 3 pictures on the defects. Kindly take
>
> >>>> a look at them and would appreciate some feedback on the possible
> >>>> root cause.
> >>>>
> >>>> Steve : Thanks for the downloading.
> >>>>
> >>>> Regards,
> >>>> Wee Mei
> >>>>
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