I found this information at the following sites, I am looking for
confirmation/clarification of allowable solder bumps in Flipchip for
ROHS.

http://www.pb-free.info/tac_summary.htm

http://www.dti.gov.uk/sustainability/weee/TAC_10_December.pdf

Regards,

Greg


 --- MA/NY DDave <[log in to unmask]> wrote:
> Hi Greg, IPC LF Listservers,
>
> Perhaps you could give the source document.
>
> <I have read proposed changes/addition to the annex of exemptions
> will
> include “Lead in solders to complete a viable electrical connection
> between semiconductor die and carrier within integrated circuit Flip
> Chip packages”.>
> <
> <How is this interpreted, is it all solder used for Flip Chip bumps
> (including eutectic) and not just high lead bumps?>
>
> If documented I would agree with you. All lead in solder.
>
>
> Yours in Engineering, Dave
> Y i Engr, MA/NY DDave
>
>
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=====
Greg Kowal
Vancouver, BC



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