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November 2000

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Subject:
From:
David Hillman <[log in to unmask]>
Reply To:
Leadfree Electronics Assembly E-Mail Forum.
Date:
Thu, 2 Nov 2000 07:42:14 -0600
Content-Type:
text/plain
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text/plain (134 lines)
Hi Walter! The ANSIJ-STD-002A and 003 committees have been working very
diligently to have the IEC specifications and the 002A/003 specifications
reflect minimal differences as much as possible (in a global economy it
would be nice to have specifications that agree with each other :)  ). If
Mark Kwoka and I could obtain a copy of the proposed IEC changes and the
supporting data it would be quite useful in the current committee efforts.
Please email me the proposal when available. John Porter (Multicore) and
Dr. Chris Hunt (NPL) has been a key individuals in assisting the 002A/003
committees in coordinating with the IEC solderability specifications.

Dave Hillman
Rockwell Collins/ ANSIJ-STD-002A/003 CoChairman
[log in to unmask]




Walter Huck <[log in to unmask]>@IPC.ORG> on 11/02/2000 02:44:35 AM

Please respond to "Leadfree Electronics Assembly E-Mail Forum."
      <[log in to unmask]>; Please respond to [log in to unmask]

Sent by:  Leadfree <[log in to unmask]>


To:   [log in to unmask]
cc:

Subject:  Re: [LF] Standard Method for Solderability Testing





Dear LF colleagues,
here in Germany we havd asked us the same question some month ago. As
result a
task force of the German National Standardization Committee (DKE) prepared
a
proposal for testing components designed for lead free soldering processes.
This document is based on the IEC 60068-2-58 (Test methods for
solderability,
resistance to dissolution of metallization and to soldering heat of surface
mounting devices (SMD)).

It proposes the following test conditions
Solderability:   245°C / 3s (solder bath method);  245°C / 10s (reflow test
method); solder SnAgCu
Resistance to soldering heat:  245°C / 40s (reflow method), or, 260°C / 10s
(reflow or solder bath method), or, 280°C / 5s (solder bath metho, for high
temperature soldering processes only).

The discussions, which already took place, have shown that these conditions
on
one hand do reflect the LF process conditions, which are actual under
consideration at many users, but, on the other hand, there are many
electronic
components which cannot withstand these conditions. (E.g. larger ICs,
electromechanical components, etc.). This has to be considered by the
designers
of LF equipment and LF soldering processes.

The document will be issued to IEC within this month, and I will distribute
it
in this forum afterwards for further discussion.
Looking forwards for your comments.

regards




Clark Smith <[log in to unmask]> on 11/01/2000 08:56:28 PM

Please respond to "Leadfree Electronics Assembly E-Mail Forum."
      <[log in to unmask]>; Please respond to Clark Smith
      <[log in to unmask]>

To:   [log in to unmask]
cc:    (bcc: Walter Huck/GER/MURATA_EUR)
Subject:  [LF] Standard Method for Solderability Testing



  I am looking for a solderability test method for evaluating
components with lead free terminations that are to be used for lead
free electronic assembly.
  Is there a released / revised test method available for solderability
testing?  Possibly a revision to MIL-STD-202 Method 208 or EIA-
575 Paragraph 3.12.
  If not, is there an industry standard making group that is working on
such a test method?  Who?
  Any related input would be appreciated.
  Thanks,


Clark Smith
Director of New Product Development
Vishay Dale
Columbus, Nebraska  USA
Phone:  (402) 563-6670
FAX:  (402) 563-6584
Email:  [log in to unmask]

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Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives
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information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
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