Dear Mr.Huck,
I agree with Solderability test method which you propose.
The temperature, 245degC, is very good for testing.
However, I think that the heat-resisitance of reflow which you propose is
severe.
It is difficult to distribute so many electronic components at the reasonable
cost.
I propose the following heat-resistant test conditions of reflow.
1.The standard of heat-resisitanec should be divided into three.
2.As for one in them, the peak temperature is 260degC.However, you have to get
expensive components.
3.2nd test condition has the peak temperature is from 245 to 250degC.
4.3rd is conventional.You have to use low melting point solder such as Sn-Bi and
Sn-Zn, but cost of components are same as now.
I have a question for you.
Is test method which you proposed examined at a constant temperature of 245degC?
I think that you should divide pre-heating and the soldering temperature.
Regards,
ICHI SAKAMOTO
Walter Huck <[log in to unmask]> on 2000/11/02 17:44:35
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"Leadfree Electronics Assembly E-Mail Forum." <[log in to unmask]> $B$KJV?.$7$F$/$@$5 (B
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cc: (bcc: ichizo sakamoto/OMRONJP)
$B7oL> (B: Re: [LF] Standard Method for Solderability Testing
Dear LF colleagues,
here in Germany we havd asked us the same question some month ago. As result a
task force of the German National Standardization Committee (DKE) prepared a
proposal for testing components designed for lead free soldering processes.
This document is based on the IEC 60068-2-58 (Test methods for solderability,
resistance to dissolution of metallization and to soldering heat of surface
mounting devices (SMD)).
It proposes the following test conditions
Solderability: 245 $B!k (BC / 3s (solder bath method); 245 $B!k (BC / 10s (reflow test
method); solder SnAgCu
Resistance to soldering heat: 245 $B!k (BC / 40s (reflow method), or, 260 $B!k (BC / 10s
(reflow or solder bath method), or, 280 $B!k (BC / 5s (solder bath metho, for high
temperature soldering processes only).
The discussions, which already took place, have shown that these conditions on
one hand do reflect the LF process conditions, which are actual under
consideration at many users, but, on the other hand, there are many electronic
components which cannot withstand these conditions. (E.g. larger ICs,
electromechanical components, etc.). This has to be considered by the designers
of LF equipment and LF soldering processes.
The document will be issued to IEC within this month, and I will distribute it
in this forum afterwards for further discussion.
Looking forwards for your comments.
regards
Clark Smith <[log in to unmask]> on 11/01/2000 08:56:28 PM
Please respond to "Leadfree Electronics Assembly E-Mail Forum."
<[log in to unmask]>; Please respond to Clark Smith
<[log in to unmask]>
To: [log in to unmask]
cc: (bcc: Walter Huck/GER/MURATA_EUR)
Subject: [LF] Standard Method for Solderability Testing
I am looking for a solderability test method for evaluating
components with lead free terminations that are to be used for lead
free electronic assembly.
Is there a released / revised test method available for solderability
testing? Possibly a revision to MIL-STD-202 Method 208 or EIA-
575 Paragraph 3.12.
If not, is there an industry standard making group that is working on
such a test method? Who?
Any related input would be appreciated.
Thanks,
Clark Smith
Director of New Product Development
Vishay Dale
Columbus, Nebraska USA
Phone: (402) 563-6670
FAX: (402) 563-6584
Email: [log in to unmask]
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