Hi Phil,
For you, I care to.  Here is my recollection and opinion:

Fabricators and others resisted specification on three grounds:
1) assumption that said cracks don't propagate
2) liability of the design activity wrt designs which have electrically biased z-axis predisposition to the failure mechanism
3) thermal zone

In my opinion, it is indeed likely that the cracks as (optically observed) don't propagate.
However, I think the history of the thermal zone is totally dependent upon the assumption of all conductors in the neighborhood being at the same potential.
Moreover, dielectric breakdown does certainly propagate and would have a strong affinity to the stress concentration points.

I would suggest that a tenable solution at this time would be to design a test vehicle (or sacrifice actual board) which would undergo the MIR/DWV routine as the E coupon does know, except after 2.6.27.  Additional upside: for sequential laminations, it would actually bring some value back to the test.

My two cents

Chris



Chris Mahanna
President, Technical Manager
Robisan Laboratory Inc.
6502 E. 21st Street
Indianapolis, Indiana 46219
317-353-6249






-----Original Message-----
From: IPC-600-6012 [mailto:[log in to unmask]] On Behalf Of Whittaker, Dewey (EHCOE)
Sent: Monday, August 30, 2010 11:32 AM
To: [log in to unmask]
Subject: Re: [IPC-600-6012] Thermal Zone Definition

I agree with Phil. This is an important topic that needs to be addressed
along with other issues that were tabled and not in the C revision.
Dewey

-----Original Message-----
From: IPC-600-6012 [mailto:[log in to unmask]] On Behalf Of Philip M
Henault
Sent: Friday, August 27, 2010 12:42 PM
To: [log in to unmask]
Subject: [IPC-600-6012] Thermal Zone Definition

Now that it's been quiet for almost a day.....

One of the things that this committee left on the shelf when trying to
get
out Rev C was the issue of properly defining the thermal zone with
respect
to blind, buried and micro via structures.  I have attached a few photos

provided by Bill Reed to illustrate the concern.  As a committee, we
need
to address the condition depicted in these photos and apply an
appropriate
post thermal stress requirement.  If I'm not mistaken, the coupons that
these photos were taken from were all stressed IAW TM-650, Method 2.6.8
(10 second solder float @ 550F).  My preference would be to not extend
the
thermal zone definition below the via structure because I do not want to

compromise minimum dielectric spacing however, I realize that some
materials may be up to the task.  I know this is on the Agenda for the
Midwest meeting but, should anyone care to weigh in now it would be
appreciated.



        Phil


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