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June 2002

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Subject:	Re: Dielectric Withstanding Voltages
From:	"Martinez, Rene" <[log in to unmask]>
Reply To:	(Combined Forum of D-33a and 7-31a Subcommittees)
Date:	Fri, 14 Jun 2002 09:05:20 -0700
Content-Type:	text/plain
Parts/Attachments:	text/plain (31 lines)

Both.

-----Original Message-----
From: John Perry [mailto:[log in to unmask]]
Sent: Thursday, June 13, 2002 8:04 AM
To: [log in to unmask]
Subject: [IPC-600-6012] Dielectric Withstanding Voltages

Colleagues,

I had posted a query from the Embedded Passives Performance Task Group concerning dielectric withstanding voltages but to date have not received any reply.  Please take a moment to review the following question and provide some clarification that we can provide the EPPTG as they work on the IPC-6017 draft:

The D-37c Embedded Passive Devices Performance Specification Task Group, responsible for developing the IPC-6017 for embedded board performance, would like to clarify our intent with Table 3-10 in the IPC-6012a on dielectric withstanding voltages:

Does this table apply to spacings between conductors on a layer, or to layer-to-layer spacings, or both?

Best Regards,

John Perry
Technical Project Manager
IPC
2215 Sanders Road
Northbrook, Il 60062
1-847-790-5318 (P)
1-847-509-9798 (F)
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