I would not think so, a run is neither to be soldered, nor exposed, if it is
supposed to be covered with solder mask. 3.8.1 addresses the situation where
a mask is broken or may break in the process and solder bridge between the
conductors creating a electrical short could/would occur.
The other one actually talks to a situation where there is probably a skip
in the soldermask over a spot and the  spot takes solder as a result. That
is a cosmetic defect and does not affect the functionality of the board.

----- Original Message -----
From: "John Perry" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, May 08, 2002 2:45 PM
Subject: [IPC-600-6012] EXPOSED COPPER/FINAL FINISH


Do we have a conflict here within the IPC-6012a?


In IPC-6012a, Section 3.5.4.6, it states that exposed copper on areas not to
be soldered is permitted on 1% of the conductor surfaces for Class 3 and 5%
of the surfaces for Class 1 and Class 2.

But, Section 3.8.1 Solder Resist Coverage sub-paragraph a.  states "Metal
conductors shall not be exposed or bridged by blisters in areas where solder
resist is required."

The percent allowance issue has been discussed before at Expo 2001 but we
did not walk away from that meeting with a clear cut definition of what
constitutes X percentage on a board, let alone potential conflict with
section 3.8.1.

Best Regards,



John Perry
Technical Project Manager
IPC
2215 Sanders Road
Northbrook, Il 60062
1-847-790-5318 (P)
1-847-509-9798 (F)
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