Bill:
We don't do much bed-of-nails testing, but it is company policy to make sure the boards are 100% testable "just in case". Most testing (especially on the more complex boards) is JTAG and functional testing at EOL, since bed-of-nails wouldn't catch a whole lot.
Cadence has built in automation for bed-of-nails testing. It will replace vias with the test via specified in the net's physical constraint set, based on user selection of test strategy and values in a constrains form that specifies spacing, grid, etc. It also allows attaching a NO_TEST property to nets that don't need a testpoint. This rarely achieved 100%, but it allows you to go thru and manually place testpoints (including single sided ones) to catch remaining nets. There is a shareware SKILL language program to highlight nets missing at least one testpoint that helps this process significantly.
I am sure most higher level tools do this, and probably a lot of the lower end, too.
--
George Patrick
Tektronix, Inc.
Central Engineering, EDS Application Support
P.O. Box 500, M/S 39-512
Beaverton, OR 97077-0001
* 503-627-5272 (voice) * 503-627-5587 (fax)
http://www.tektronix.com <http://www.tektronix.com/> http://www.pcb-designer.com <http://www.pcb-designer.com/>
"Off grid and Proud of it!"
________________________________
From: DesignerCouncil on behalf of Brooks,Bill
Sent: Tue 6/5/2007 5:15 PM
To: [log in to unmask]
Subject: [DC] ICT, bed-of-nails and CAD tool support?
'In-Circuit Test' is a seldom discussed subject at the 'designer's round
table' here...
I'm curious how other designers are affected by test points and how they
deal with testability in their designs.
I have placed test points in schematics and treated them as 'components' on
the board before...
What have you seen for test point support from the CAD vendors and is there
an easy way to automate this?
Also those who have to test for a living... what is the process you use and
are the outputs from these CAD tools any help?
Best regards,
Bill Brooks, CID+
---------------------------------------------------------------------------------
DesignerCouncil Mail List provided as a free service by IPC using LISTSERV 1.8d
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF DesignerCouncil.
To temporarily stop/(restart) delivery of DesignerCouncil send: SET DesignerCouncil NOMAIL/(MAIL)
Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives
Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
DesignerCouncil Mail List provided as a free service by IPC using LISTSERV 1.8d
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF DesignerCouncil.
To temporarily stop/(restart) delivery of DesignerCouncil send: SET DesignerCouncil NOMAIL/(MAIL)
Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives
Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815
---------------------------------------------------------------------------------
|
