Tom, 

One more item to ask:
What is the required plating in the hole - Cu thickness? 
What is the finish thickness - Ni thickness? Au thickness?
Are the vias covered / plugged with soldermask?

Issues to think about are:
Too little plating in the via hole
Trapped corrosives in the hole 

Thanks
Tony Cosentino
Tekelec
919-460-3656
[log in to unmask]

-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Tom
Parkinson
Sent: Tuesday, June 05, 2007 10:14 AM
To: [log in to unmask]
Subject: [DC] Via Open

Tech Net & Designer Net

Greetings. We are running into a situation on Lead Free processed PCBs.
Failure mode is finding open vias during unit testing (fully populated).

Boards are Tg170, Material type EM320, 0.063" thick boards.  
6 layers of 1 oz copper. ENIG 3~5u"

Suspect vias go from top layer to bottom layer only.

After running through reflow, we have found vias open. No visual signs
of delamination, however when ohming out the via, if we press on the via
we get continuity - thus we suspect the vias are opening during the
process.

Anyone out there having these problems, or information concerning this
failure mode?  Z-expansion failure?


Tom Parkinson
Quality System Manager - CIT
WinTronics, Inc.
Phone: 724-981-5770 - extension 235

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