maybe I'm having a "not enough coffee yet" morning,
but I was asked how much separation I need between layers for high voltage.

We have a design that may have 1700V in several places.
Since we are looking at a clearance into the board, layer-to-layer
I'm pretty sure I can use the "internal" column B1 of Table 6-1 in IPC-2221
(using Table 6-1 for z-axis was discussed in a committee meeting and no one
disagreed)

but the number I get for 1700V is =
(.25 mm for the first 500V) plus (.0025 mm for each of the other 1200V, 3
mm)
equals 3.25 mm

For one thing, it already seems like I'm off-track because .25 for 500V
doesn't correspond very well with 3 mm for 1200V, but if you can't trust
IPC..... well, let's not go there.

My REAL question is that, although I'm safe using 3.25 mm, my board is not
that thick!
Is there a smaller z-axis clearance that can be used for 1700V? across
typical FR4 material?
(we are using a RoHS compatible 170Tg /126)

What's the MINIMUM layer spacing I can use for 1700V?

thanks,
Jack


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