Hi all,

I recently had this response from my fabrication house, and was wondering
if anyone else has run into this issue. I'm still trying to figure out
exactly what it means (e.g. costs me).

----------------------------
Due to blind vias/epoxy fill requirement & spacing on the outer layers, a
new copper wrap plating process cannot be achieved per IPC 6012B due to
spacing issues. I would like to verify if we can wave this process since
you have less than 4 mils space on your data. Please see below.

In mid January of 2007, IPC released Amendment 1 of 6012B, updating it's
copper wrap plating spec (3.6.2.11.1) that reads as follows:

Copper wrap plating minimum as specified in Table 3-2 shall be continuous
from the filled plated hole onto the external surface of any plated
structure and extend by a minimum of 25 um (984uin) where an annular ring
is required.  Reduction of wrap-plating by processing (sanding, etching,
planerization, etc.) resulting in insufficient wrap plating is not
allowed.
XXX1 is committed to manufacturing your PCB's to the highest standards.
Due to the panelizing process, designs requiring a space of 4 mils or
smaller can not be built to this spec.
----------------------------

Thanks in advance.
Mitch


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