John,
I agree with your pad/hole size, with one exception - It is not recommended
to allow the hole to plate shut. Due to the fact that the hole plates
faster near the PCB surfaces than it does in the middle, contaminants can
get trapped inside the (sometimes) resulting void at the middle of the hole.
The severity of this can vary, depending on PCB thickness. Later, such as
during wave soldering, these trapped fluids expand, causing barrel cracking
and other problems. These trapped fluids can also cause other problems, if
they ever leak out. I use a tolerance of +0.003/-0.007, which will ensure
that the holes are open to be flushed and drained. The holes can later be
filled with solder during the wave soldering process.
Regards,
Ray
----- Original Message -----
From: John Laur <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, November 11, 1999 1:38 PM
Subject: Re: [DC] Via Padstack
> Rich,
> I typically use a 0.012 +0.003/-0.012 finished (Allow the via to plate
shut)
> with a 0.025 pad.
> My vendor can do finished hole diameter + 0.014
> He would drill at 0.016 (no cost hit) and plate back to 0.011 add the
0.014
> and you get 0.025.
>
> I agree with Cyrus on the test pad size at 0.035. Build your via with a
0.025
> on all layers except the probed layer which could be 0.035.
>
> John Laur
> Sr. Technical Analyst, PCB Design
> Rockwell Automation / Allen-Bradley
> 1201 S. 2nd St.
> Milwaukee, Wi 53110
>
>
>
>
>
> Cyrus Ringle <[log in to unmask]> on 11/11/99 02:07:14 PM
>
> Please respond to "DesignerCouncil E-Mail Forum."
<[log in to unmask]>;
> Please respond to Cyrus Ringle <[log in to unmask]>
>
> To: [log in to unmask]
> cc: (bcc: John C Laur/Milwaukee/RA/Rockwell)
> Subject: Re: [DC] Via Padstack
>
>
>
> Rich,
>
> If you are planning to do ICT "In Circuit Test" you may want to use these
Vias
> as test sites. So I would suggest using .035 so it could be probed on the
> bottom of the board "secondary side" by a test fixture. If you are not
testing
> the real answer for the min. can be answered by the fabrication vendor.
Using
> .032 meets IPC spec.
>
>
> Cyrus Ringle
> Sr. CAD Specialist
> Inter-Tel, Inc. http://www.inter-tel.com
> 7300 West Boston Street
> Chandler, AZ 85226
> Voice: (480) 961-2263
> Email: [log in to unmask]
>
>
>
>
> Rich Klecka <[log in to unmask]> on 11/11/99 09:33:01 AM
>
> Please respond to "DesignerCouncil E-Mail Forum."
<[log in to unmask]>;
> Please respond to Rich Klecka <[log in to unmask]>
>
> To: [log in to unmask]
> cc: (bcc: Cyrus Ringle/Inter-Tel)
> Subject: [DC] Via Padstack
>
>
>
> I am making up a via padstack that has a 12 mil finished drill
> diameter. I want to keep the pad size as small as possible. What pad
> size would you use for routing layers and for power plane layers?
> Minimum trace width will be 8 mils.
>
> Thank you for your help,
> Rich
>
> --
> Rich Klecka
> Electronic Packaging Specialist
> Fermilab
> P.O. Box 500, M.S. 307
> Kirk & Wilson Roads
> Batavia, IL 60510
> [log in to unmask]
> 630-840-3880 Phone
> 630-840-8590 Fax
> Work hours: 8:00 - 4:30 Central Time
>
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