The epoxy/glass dielectric actually is spec'd at 750V per mil insulation resistance perpendicular to the layers according to Mil-P-13949/4C for FR4 glass epoxy laminated materials. So 1.3 mils minimum of material perpendicular to the layers would net you 1KV insulation resistance top to bottom or internal layer to layer.
Always give yourself some margin... The back side of the copper foil is rough and can be 'spiked' on the laminated side for foil adhesion... those spikes can cause the spacing to be less than the minimum target spacing you require when laminated. Also there can be bubbles or voids in the materials that could occur right between your two high voltage conductors... Unless you are trying to mimic a capacitance plane pair, there is little or no reason to have the high voltage lines that close. You don't want a short to occur internally in the board. Give yourself a buffer of at least a couple of additional layers of 2 mil prepreg on internal layers. Just saying... :) Good design practice is to de-rate by 50%.
I don't warranty sharing my observations... or advice... but if you feel the need to compensate me... I like microbrewery beers... the Darker Belgian style... I'm not a big hops lover... though I like the hoppy beers too just not as much... :)
William Brooks, CID+
Senior MTS (Contract)
2747 Loker Ave West
Carlsbad, CA 92010-6603
760-930-7212
Fax: 760.918.8332
Mobile: 760.216.0170
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-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Jack Olson
Sent: Friday, June 20, 2014 7:35 AM
To: [log in to unmask]
Subject: [DC] z-axis separation for high voltage
maybe I'm having a "not enough coffee yet" morning, but I was asked how much separation I need between layers for high voltage.
We have a design that may have 1700V in several places.
Since we are looking at a clearance into the board, layer-to-layer I'm pretty sure I can use the "internal" column B1 of Table 6-1 in IPC-2221 (using Table 6-1 for z-axis was discussed in a committee meeting and no one
disagreed)
but the number I get for 1700V is =
(.25 mm for the first 500V) plus (.0025 mm for each of the other 1200V, 3
mm)
equals 3.25 mm
For one thing, it already seems like I'm off-track because .25 for 500V doesn't correspond very well with 3 mm for 1200V, but if you can't trust IPC..... well, let's not go there.
My REAL question is that, although I'm safe using 3.25 mm, my board is not that thick!
Is there a smaller z-axis clearance that can be used for 1700V? across typical FR4 material?
(we are using a RoHS compatible 170Tg /126)
What's the MINIMUM layer spacing I can use for 1700V?
thanks,
Jack
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