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March 2005

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Subject:
From:
"Post, Devon J." <[log in to unmask]>
Reply To:
(Designers Council Forum)
Date:
Tue, 15 Mar 2005 07:56:25 -0600
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text/plain (88 lines)
Scott,

Depending on the actual CAD/schematic entry tool that you are using, some of
them have the capability to partition a schematic symbol into multiple
parts.  This allows you to have for example, a power/gnd section, a high
speed I/O section, and a low speed I/O section.

If you are trying to create a schematic symbol for a CPLD, or an FPGA this
can be more complicated.  You could break them up by functional groups, or
banks, or ease of external routing depending on interaction with the person
creating the implementation of the device.

I have personally both partitioned a part, and created a schematic with one
very large symbol to represent a high I/O count part.  The partitioned way
is by far easier, but it can be done.  The latter is probably harder to read
from a size perspective.  Again it all comes down to the tool that you are
using.

Hope this helps,
Devon

 =======================================================================
Devon J. Post - C.I.D.                           Mayo Foundation
<mailto:[log in to unmask]>                   200 First Street SW
Voice:  (507) 538-5479                           Sn 2-134C
Fax:    (507) 284-9171                           Rochester, MN 55905
Internet:  http://www.mayo.edu/sppdg/sppdg_home_page.html
 =======================================================================



-----Original Message-----
From: Scott Riley [mailto:[log in to unmask]]
Sent: 15 March, 2005 7:47 AM
To: [log in to unmask]
Subject: [DC] Schematics for high pin count BGA devices


I'm looking for a little information on the best way to represent BGA
components with a high pin count (EX: 484 I/O) in a schematic. I need to be
able to document a schematic for a board that will have two BGA devices (484
I/O and 165 I/O). Once the customer reviews/approves the schematic I would
extract a netlist and use it to create rats on the layout and for
programmatic comparison.

My assumption is that I will need to create symbols that have all the pins
around the perimeter of a square or rectangle, but was hoping someone could
share their  experience on schematics for similar components and if there is
a better/different approach.


Scott D. Riley
Technical Design Service
607-658-9322 - Office
607-785-1696 - FAX
 <http://www.techdesignservice.com/> www.techdesignservice.com







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