Steve,

I was trying to say that instead of trying to squeeze in routes on the top
and bottom of a layout, (also I'mm assuming 1 pwr and 1 gnd layer) , and perhaps
having to go to 4 mil trace widths - it is better to just run the critical stuff
on top and bottom, make the pwr and gnd layers (2 and 5) to have nice microstrip
impedances - then just hit the router for the two inner layers using 6 mil widths.

This allows the layout to move quch more quickly during the prototype stages - 
where speed of delivery for testing initial circuits is more important than
consideration for high volume - and I believe the cost of teh additional two
layers is justifiable. 

The quality standpoint I also refere to is the fact that yields improve if you
use thicker path widths and larger clearances. typically. Of course I'm talking
from widths/clearances of 6 and higher inner, 8 or higher outers.
as much as the bb suppliers tout that 4 mil isn't a yield hit on outer layers,
I believe that the cost to cover their yeilds is about 10 - 20% - so that the
savings to go to 4 layers isn't "true" savings

In addition - the 4 layer would have 1100 more vias and most likely smaller diameters
and pads - which should be minimized whenever possible. I don't know what this product
is and the qtys or the time to market so it's hard to generalize, but I have been
successful is using this approach/philosophy in what we do here at Bell Labs.


Your thoughts are welcome.
Tom Kavendek
Lucent Technologies - Bell Labs
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