Here is an old one I used to use a long time ago I hope it helps some.
Mechanical
1. Board Profile is fully dimensioned (view orientation is defined from
component side.)
2. Mounting holes are defined and fully dimensioned with their size, plating
type, clearances and detailed with any special grounding requirements.
3. Keep-out areas and restricted areas are dimensionally located and defined
as to the type of restriction involved; (i.e. component height, component
location, no route areas, etc.)
4. Parts that must match off board locations such as bezels or connectors
are clearly defined and their locations fully dimensioned for mating part
alignment and correct pin orientation match up.
5. Any special mechanical components such as stiffeners, heat sinks, wiring,
ground straps, gaskets, part sockets, special shielding, etc. are clearly
defined and fully dimensioned with their location, mounting holes, mounting
hardware and any attachment requirements.
6. Clearance areas that must be kept clear of solder mask, conformal
coatings, paint, etc. detailed and dimensioned.
7. Airflow direction and force is described and shown.
8. Review Bill of Materials (BOM) for correct connectors, mounting hardware,
heat sinks, and any mechanical part issues. Note to check exploded component
assemblies with multiple line items.
9. Detail any type of nomenclature or notes to be added to the board or
schematic.
10. All dimensions are referenced off of a tooling hole (0.125 diameter
non-plated) designated as point of origin, and point of origin tooling hole
is dimensioned to closest lower left board edge location.
11. Non-standard or special methods of part attachment such as adhesives,
rivets, etc., or specified order of attachment for any mechanical hardware
described in BOM or detailed on drawing.
12. Define any requirements for copper weight for traces, finished board
thickness, solder mask type and color, silkscreen color, board finish
(immersion silver or gold, HASL, etc), board material.
13. Board stack up information is defined for number of layers, stack up
requirements (signal layers-plane layer relationships, etc.).
Thermal
1. Heat sensitive or heat radiating components identified and layout
limitations denoted on schematic. Part orientation checked to verify airflow
is not being obstructed or blocked.
2. Air flow and direction calculated against PCB card profile and thermal
placement profile derived and sent to CAD.
3. Environmental stress conditioning requirements to meet MTBF requirements
are detailed and sent to CAD.
4. Component de-rating guidelines defined and BOM reviewed for compliance.
5. Hot parts requiring heat dissipaters or heat sinks noted on schematic
and BOM.
6. Are thermal core planes required or any other special thermal controls
needed?
Components
1. BOM reviewed for availability of components, alternate vendors, etc. Long
lead time components flagged and alternatives suggested.
2. Components having manufacturing problems, reliability problems, or cost
issues flagged and alternatives suggested.
3. BOM reviewed for adherence to compliance, thermal de-rating, test, and
assembly standards and specifications.
4. Board number, rev level, title, used on, next assy number, module
number, etc., are correct.
5. Pending ECO changes have been included or considered.
Electrical
1. Generation of schematic in Mentor Graphics Design Capture.
2. Schematic is drawn keeping logic functions, logic families, or logic
devices with similar power and signaling characteristics grouped together.
3. Components being used for the first time have had their symbol and cell
relationships checked for correctness. (i.e. pin mapping, pin names, cell
size, mounting leads grounded, alternate vendor cell compatibility, etc.).
Ensure that polarized parts are symbol-cell matched for polarity.
4. Rules controlling PCB layout clearly stated as notes on schematic or
embedded into database used to produce layout.
5. PWB layout locations of critical component placements such as decoupling
capacitors, terminating resistors, crystals, buffers, parts dissipating over
1 watt, etc., shown on the schematic or referenced in schematic notes.
6. Pending changes or rework issues on previous boards or similar types of
boards considered and implemented on schematic.
7. Component manufacturers PCB layout application notes transcribed as
notes on schematic.
8. Spares, phantom part chart, bulk-decoupling capacitors for all reference
voltages and grounds, and unused gates with termination schemes detailed on
last page of schematic.
9. Schematic pages brought in from other designs used on this design have
been reviewed for content accuracy, elimination of redundant circuits,
consistent signal net and global net naming conventions, device type
availability, reduction of part types by combining similar device types into
one part number/package type, or pending rework issues, etc.
10. If embedded resistors or capacitors were used check BOM to make sure
their quantity is zero so purchasing does not try to purchase them.
11. Critical nets, transmission lines, differential pairs, high voltage
lines, clock lines, impedance controlled lines, etc., have their PWB layout
routing rules such as trace width/spacing/length, routing layer guidelines
(i.e. layer stack up, power/ground plane assignments, reference return
planes, layered routing pair sequences, restricted layer routing, etc.),
conductor routing topology strategy (i.e. star route, tee route, H route,
daisy chain, terminations, stub lengths, etc.), etc. denoted on schematic or
specified as special instructions to CAD.
12. Any industry standards or specifications that need to be adhered to are
denoted on schematic.
13. If any nomenclature designations need to be silk screened on PCB denote
them on schematic. (i.e. logic function naming of connectors, designated
board areas, headers, jumpers, logic probe points, test points, etc.)
14. If headers, connectors, or jumpers have multiple connection
methodologies, ensure that connection information is shown on schematic and
noted to be silk screened on PCB.
15. Components with JTAG capability are designated on schematic as being
JTAG compliant.
16. Review schematic for any thermal related issues and denote them on
schematic.
17. Ensure that nets going to other locations and not labeled as global
nets use intra-page symbols if they only continue on the same page, and
inter-page connector symbols if they continue off page, and that the net
cross reference utility command has been run.
18. Review schematic for readability, no text crossing lines, all notes
complete, title block area complete, page numbering, rev level, hierarchical
blocks and pages labeled with correct names, etc.
19. Schematic completed, verified, compiled and packaged.
20. BOM generated and checked for completeness. Review BOM for correct
connectors and consider if connectors mate pin-to-pin with mating connector,
check for proper mounting hardware, heat sinks, or any mechanical part
issues. Check especially for any required mechanical parts not automatically
produced by schematic BOM generation.
Signal Integrity
1. IBIS model library maintained and source files for models provided.
2. Results of simulations and tests documented.
3. Software , computer simulation methods, and physical test setups used for
profiling have been documented.
4. EMI sensitive components, EMI radiating components, maximum current
circuits, maximum voltage circuits, high gain circuits, matched length
circuits, clock skewing circuits, global power filtering scheme, device
power filtering scheme, critical circuits, clock lines, circuit shielding
requirements, grounded heat sinks, circuits requiring close association or
separation rules, differential pairs, controlled impedance, transmission
lines, layer stacking, etc., are detailed on schematic.
5. EMI threshold report generated and specifications for proper EMI and SI
compliance documented.
6. Distribution of all relevant data to applicable parties.
Assembly
1. Direction of assembly board or panel through wave solder shown on
mechanical board profile drawing.
2. Assembly panelization drawing provided to CAD.
3. Tooling holes and PWB and component fiducials located and dimensioned.
4. Secondary operations identified and documented.
5. Parts requiring added assembly instructions like fragile components made
of glass or ceramic requiring sleeving or embedding, parts sensitive to
ultrasonic cleaning (i.e. crystals, diodes, etc.), heavy or large parts
requiring mechanical restraint, parts easily damaged by ESD, header
connection details, etc., are reviewed and assembly requirements given to
CAD.
Test
1. Effort made to select VLSI devices that have JTAG capability. A must on
all BGA devices.
2. Was a provision made for a single contiguous scan path that will connect
all devices having JTAG capability.
3. Was option to connect daughter and paddle cards into contiguous JTAG
path.
4. Addressable scan port device implemented to provide a slot number based
scan address unique to each module.
5. Connectors provided to access micro controller address and data lines ,
as well as other signal lines need to put controller in an inactive state.
6. Internal loop-back capability has been provided on bearer busses to allow
processor to determine of board circuitry is functioning properly.
7. Has a plan to have embedded ROM/RAM tests to be incorporated that allows
execution by system software at power up been devised.
8. Is a serial EEPROM incorporated in design and all signals from the serial
EEPROM available on the same connector.
9. Have provisions to program all CPLD, GAL, ISP, or other RAM devices
through JTAG or other means.
10. In addition to main, paddle, or daughter card are any other test
connectors needed.
11. Has a plan to program software checksums in to flash and other ROM
devices been implemented. There should be a single checksum for each device.
Checksum will be derived from all program, data, and firmware information
storied in each device.
12. Notes for test point sizes (.025 sqr or .025 dia) and nets used for ICT
detailed on schematic.
13. Review of all accessible points for 100% testability.
14. On modules testing shall be done by JTAG, test connectors, embedded
tests, and PC based control software.
15. On sub-modules testing shall be done by JTAG, main module with embedded
software used for test bed, and PC based control software.
16. On paddle cards use ICT.
17. On power supply modules use functional tests only.
18. Does an existing test fixture exist that any board changes must keep
current Test Point locations.
Compliance
1. Required compliance specifications and standards are detailed as notes on
schematic.
2. Nets requiring compliance rules are denoted on schematic, and their
compliance issues such as external/internal etch widths and spacing, high
voltage layout rules, ground stitching guidelines, etc., are detailed as
well.
3. Requirements for tip and ring voltages, high pot, EMI, ESD, ground
straps, etc., have been thought out and detailed as notes on the schematic.
Consider this as a starting point.
Glenn
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]]On Behalf Of
Pucket, Larry Lee
Sent: Thursday, December 13, 2001 2:36 PM
To: [log in to unmask]
Subject: [DC] Design Checklist
Anyone out there willing to share with me their checklist that they go thru
when a new job comes in from a customer for a pcb to be designed for a
customer. Such things as no. of layers, current capability, board size,
controlled impedance, etc.
Larry L. Pucket
[log in to unmask]
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