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September 2014

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From:
"[Jeffrey] [Jenkins]" <[log in to unmask]>
Reply To:
(Designers Council Forum)
Date:
Fri, 12 Sep 2014 16:07:44 +0000
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Viasystems and TTM both perform this process for me since 2007.  Viasystems official name is "Solid Copper Through-Hole".  
I use it in place of epoxy via fill for when I need the utmost thermal conductivity and have limited space or am using a conduction only (meaning limited to no air-flow) as a heat removal from a design.

Cost wise:  it's about a wash with Epoxy fill.  There are less steps, but it takes more time in the bath to plate up.  I've done it with .080" boards with .010 holes, and I've also done it with a .080" seq-lam with all the buried and through hole vias plated solid.  All successfully and in production runs, not just protos.

Design issues:  
- They are plated solid, with limited to no voids.
- They are very robust, the material surrounding them will generally give out first before they do.  
- Use with caution as via-in-pad.  They are excellent heatsinks.  You will  be able  to put down a device (BGA) during reflow with them in the pad, if they are connected to planes without thermals  you'll have a difficult time getting the device back up if you have to R/R it (lesson learned here).  If you use them in a pad and they connect to a planes, make sure to put thermals on them.
- QA folks may have an issue as the wrap plating is a little different with these.  There really should be a separate section in the IPC-A-600 for them.  
- I've not had a failure with these vias. 

With regards to via fill in general, if I don't have to do it I don't.  I will leave the vias open top and bottom to ensure they don't entrap chemistry from the fab,  nor (and just as importantly) the the assembly process.  I've seen instances where soldermask coverered lands were not as robust as people thought and it trapped water-souble flux and caused electromigration/dedritic growth.

But if I'm stuck with devices with bottomside thermal plane connections (QFNs for example with large thermal pad and window paned), then I fill and cap.  Its part of the price of using these part in my opinion.  Yes there are methods of trying to avoid the via fill, but this method I've had the best luck with.  

Best Regards,

-Jeffrey

Jeffrey A. Jenkins CID+,CIT
Senior PCB Staff Designer || L-3  Linkabit || Ph: 858-552-9832 || [log in to unmask]


-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Brooks, William
Sent: Friday, September 12, 2014 7:30 AM
To: [log in to unmask]
Subject: Re: [DC] Vias

I was referring to the type of via that they plate solid with copper all the way thru... 
Maybe copper 'filled' is not the correct term for that type of via?

Via Systems/DDI does this process... I believe... as do a few others...

http://www.google.com/patents/US20080196935

http://www.dowelectronicmaterials.com/products/printed_circuit_boards/hdi/microfill_thf.htm



William Brooks, CID+
Senior MTS (Contract) 
2747 Loker Ave West
Carlsbad, CA 92010-6603
760-930-7212
Fax:        760.918.8332
Mobile:    760.216.0170
E-mail:    [log in to unmask]




-----Original Message-----
From: Anderson, Veronika [mailto:[log in to unmask]] 
Sent: Thursday, September 11, 2014 3:58 PM
To: (Designers Council Forum); Brooks, William
Subject: RE: [DC] Vias

Bill,

Can you clarify your definition of "copper filled via"?
As far as I know, there is no via filling material that can be called a "copper fill".
As you mentioned, the thicker plating improves the thermal transfer and current carrying characteristics of via.
I've seen the drawings with a note "vias can be plated shut".
However, the conventional plating process cannot close the via completely - there is always an air gap in the middle.  
The Reverse Pulse Plating Process provides the "solid copper plated via". So far only a few PWB manufacturers do that.
If you use a solid copper plated vias in your designs, please share a name of PCB manufacturer that builds your boards.

Regards,  

Veronika Anderson C.I.D | Sr. Electrical/Mechanical Design Engineer | Excelitas Technologies

Office:  +1 626.967.9521 x 236
1330 East Cypress Street, Covina, CA 91724 USA [log in to unmask] www.excelitas.com

-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Brooks, William
Sent: Thursday, September 11, 2014 9:31 AM
To: [log in to unmask]
Subject: Re: [DC] Vias

Peter was talking with me about using vias in thermal pads and how some still leave an open aperture the size of the thermal pad for their solder paste... 
This can cause the solder paste when it melts to be wicked down the via holes starving the part for solder... depending on the diameter of the vias and how many there are... 
One method to reduce this effect is to change the stencil aperture to a pattern that avoids the vias and helps distribute the paste over the thermal pad area evenly... 
See this illustration by Texas Instruments... 

http://www.ti.com/ods/images/SNLS302D/sample_layout_DAP_snls302.png

Another thing that helps is to reduce the diameter of the via to reduce its wicking volume... smaller holes wick less... 
I have used .008 in. diameter vias for that purpose before... 

Or... you can have the via holes filled and planarized... thus no extra solder is wicked down the holes... 
Partial filling tends to cause problems... 
For example: Trapped gases will expand in the high heat of the reflow oven and cause solder balls to occur... 
This is bad for your design when installed in the electronics application it typically must work in because solder balls are conductive and can cause shorts between pins and exposed pads or get loose in vibration and bounce around to other assemblies and cause the same sort of problems.

Also I have found that filling vias with solder does not improve their thermal transfer characteristics very much... Solder is not that great a heat conductor. Copper is the best thermal conductor typically for our PCB applications... so thicker copper plating in the holes or copper filled vias are bound to be far superior for thermal transfer reasons than filling the vias with solder. 



William Brooks, CID+




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