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June 2011

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Subject:
Re: Underfill for chip scale packages
From:
Tom Garman <[log in to unmask]>
Reply To:
(Designers Council Forum)
Date:
Thu, 9 Jun 2011 06:22:44 -0700
Content-Type:
text/plain
Parts/Attachments:
text/plain (177 lines) 
A lot of these consumer products are getting good at meeting the intent of the mil/hi reliabilty requirements without a lot of the added expense.
Most of the engineers I work with have never seen a mil spec, but they know that when a guy drops his GPS, it bounces off the boat and goes in the water. When the guy fishes it out he expects it to work again.

Best Regards;
Tom G.

--- On Wed, 6/8/11, Andy Kowalewski <[log in to unmask]> wrote:

> From: Andy Kowalewski <[log in to unmask]>
> Subject: Re: [DC] Underfill for chip scale packages
> To: [log in to unmask]
> Date: Wednesday, June 8, 2011, 8:57 PM
> Makes sense. So it (corner bonding)
> would be applied to packages that are a
> bit bulky (=heavier than normal) and maybe don't have so
> many pins to absorb
> drop shock?
> 
> Thanks Steve.
> 
> Cheers........
> 
> Andy Kowalewski
> AdvantagePCB Pty Ltd
> +61 (2) 9499 4853
> 
> -----Original Message-----
> From: DesignerCouncil [mailto:[log in to unmask]]
> On Behalf Of Steve
> Gregory
> Sent: Thursday, 9 June 2011 09:06
> To: [log in to unmask]
> Subject: Re: [DC] Underfill for chip scale packages
> 
> Hi Andy,
> 
> Corner bonding, not underfill. It helps with surviving drop
> shock without 
> having to go through all the trouble of underfilling.
> Corner bonding is lots
> 
> easier to do...
> 
> Steve
> 
> -----Original Message----- 
> From: Andy Kowalewski
> Sent: Wednesday, June 08, 2011 6:53 PM
> To: [log in to unmask]
> Subject: [DC] Underfill for chip scale packages
> 
> Just saw a web knock-down of the Barnes and Noble eBook
> reader. The larger
> Chip Scale Packages appear to have underfill applied to
> each corner, which
> has me intrigued. See
> 
> 
> 
> http://www.techrepublic.com/photos/cracking-open-the-2011-barnes-noble-nook-
> e-book-reader-wi-fi/6243892?seq=35
> <http://www.techrepublic.com/photos/cracking-open-the-2011-barnes-noble-nook
> -e-book-reader-wi-fi/6243892?seq=35&tag=content;thumbnail-view-selector>
> &tag=content;thumbnail-view-selector
> 
> 
> 
> Does anyone know the criteria for this? Underfill is
> applied in flipchip
> assembly to prevent the silicon cracking because of the
> thermal mismatch in
> CTE between glass (3ppm/degree C) and pcb (FR4 at about
> 16ppm/degreeC). I
> guess the CSP might have a similar issue - no doubt the
> silicon chip inside
> the package also gets stressed as the package stresses,
> which implies that
> there isn't a lead frame to give compliance, or a FR4
> laminate interposer
> like in bga packages that doesn't need stress relief.
> 
> 
> 
> Cheers........
> 
> 
> 
> Andy Kowalewski
> 
> AdvantagePCB Pty Ltd
> 
> +61 (2) 9499 4853
> 
> 
> 
> 
> 
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