To the DC world,

Does anyone have or know how to calculate the parasitic capacitance &
inductance on vias ? Is there a formula or chart out there somewhere that
can be used to determine this.

There are two sizes of vias that I am trying to find values for and they are
as follows;

1- Pad 0.026" diameter with a finished drilled hole of 0.013" in 0.062" FR4
material. (4 & 6 layer designs)
2- Pad 0.035" diameter with a finished drilled hole of 0.017" in 0.062" FR4
material. (4 & 6 layer designs)


Regards, Greg.

Gregory E. Bordash,
Team Leader, PCB CAD Group
ATI Technologies Inc.,
33 Commerce Valley Drive East,
Thornhill, Ontario, Canada, L3T 7N6
Phone:(905) 882-2600 ext: 8370,   Fax: (905) 882-9339
Email: [log in to unmask]