I was hoping you would get an answer to this.

To me, it doesn't make sense (my knowledge
of physics is limited, to say the least), but I'm
pretty sure high voltage can arc across the
surface of a board easier than THROUGH it,
so it seems like the z-axis should be a different
value. I'm surprised to read that in para6.3

Does anyone know?
(have you gotten any private answers?)

jack





"Bundrant, Anthony" <[log in to unmask]>@IPC.ORG>
1Mar2002 11:02 AM

Please respond to "(Designers Council Forum)" <[log in to unmask]>;
      Please respond to "Bundrant, Anthony"
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Subject:  [DC] Dielectric Disconnect
Retain Until: 03/31/2002 Retention Category: G90 - Information and Reports
Caterpillar Confidential:  Green


IPC-2221, paragraph 6.3 Electrical Clearance, states: "The minimum spacing
between conductors, between conductive patterns, layer to layer conductive
spaces (z=axis), and between conductive materials (such as conductive
markings or mounting hardware) and conductors shall be in accordance with
Table 6-1, ... ."

We have a thermal plane which will see 600 volts worst case.  According to
Table 6-1, we would need roughly 20 mils of dielectric between this plane
and a routing or electrical plane layer.  Why?  The electrical strength of
polyimide from IPC-4101/42 is 29000 volts/mm (736 volts/mil).  Has anyone
had experience with this apparent disconnect between specs?

TIA,

Anthony Bundrant
Bell Helicopter Textron
Technical Resource Specialist - Electronic Packaging
817.280.8903

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