Fred,

> All,
> I don't see much discussion on just plane old design issues. I thought I
> would throw out a few topics and see if anybody is interested in discussing
> them. I am crossposting this to Pcad users and IPC Designers Council.
> 
> Has anybody been using SMT Plus land patterns? They are advertising a lib.
> for P-Cad. How do they compare to the IPC 782 Patterns?

NO.  Dont know.

> 
> What are you doing as far as via's and conductors under SMD components? I
> noticed the P-Cad lib has keepouts under the chip components. I have been
> routing traces under SMD and have not had any problems.

Traces are fine.  Vias are fine on the component side.  Vias are fine on the
solder side IF the board is double reflowed and not wave soldered.  If the 
board is wave soldered glue dots or stripes are used and could end up in a via
robbing the part of its glue.  Of course if the via is tented its not a problem.
The thing that is important is the trace to land clearance.  I use 0.008.  The
soldermask is 0.003 larger than the pad.  That gives 0.005 of mask beyond the
trace.

> 
> Has anyone needed to provide a glue dot file for mfg? I noticed that P-Cad
> has that capability but I have never had to provide one in the past. It was
> always created from the placement file.

Not for a very long time.

> 
> Silk Screen legend sizes seem to be very large on most commercial lib's
> compared to what I have been using. I seem to get away with .008 width and
> sometimes down to .060 height. What is your experience?

How about .007 width and .040 height.  Not as a standard though.  I typically
go with .008 width and .050 height.

> 
> I have just finished a Design for a client that demanded that all components
> be orientated in the same direction and also all of them lined up, nice and
> neat. Great idea if I would have had twice the board area to work with. I
> know the desireability of this but I also like to think form follows
> function. Many of the original reasons for doing this are obsolete. The
> board is finished now but I just know placing the parts for optimal routing
> would have resulted in much shorter runs, and a more functional layout. What
> is your opinion? How are you doing it?

Form follows function.  To a point.  I try to line everything up, but if it makes
for a bad routing situation I will move or rotate it.  Symmetry is a beautiful thing.

> 
> I also was prohibited from putting chip caps on the solder side, even though
> I routinely do it with other designs. Are any of you designing boards that
> are waved with chip caps on the solder side?

Yes.  Did you ask why you could'nt?  Maybe they have no means of attaching the
components to the bottom side for wave.

> 
> Regards
> Fred Pescitelli
> Phoenix Designs
> 1285 Turner Rd.
> Lilburn, GA   30247
> [log in to unmask]
> 770-923-3465
> 
> 

---------------------------
John Laur
Rockwell Automation
Allen-Bradley Co Inc.                 
1201 South Second Street
Milwaukee, WI 53204
+1 414 382 2162 (fax)
+1 414 382 2393 (phone)

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