Fred,
Thermal soldering issues are as diverse as the processes trying to solve them.
We had some pretty good luck using minimum diameter (highest aspect ratio you can get away with) vias, 12 mil or smaller tend not to wick the solder away from the wanted solder joints.
Tenting vias can cause a number of issues both at Fab and Assy with entrapped chemistries and thermal excursion explosions. Capping, plugging, planerizing, etc. are all Fab cost adders that your management may not like. Buy if the Bosses will buy in then plugging, planerizing and cap plating is by far the best soluton.
Remember it will take more smaller vias to displace the thermal energy than the larger ones but if there is no wicking or solder thieving then it works pretty good.
One of the few advantages of Pb free solders is their flow is not as good as ole 63/37 was.
Good luck,
FNK
Frank N Kimmey CID+
FNKEC
PCB Design and Consulting
Sent from my iPad
> On Apr 24, 2014, at 12:58 PM, Fred Dark <[log in to unmask]> wrote:
>
> Hello all - we have been adding a solder-mask dot on the same side as the IC's with a "GND-SLUG"... no issue... however if a "SLUG" has a large quantity of vias due to the requirement to dissipate heat here is where I have a issue... not enough area for paste and proper solder percentage to the area... so in this case I was suggesting to tent the opposite side that the IC resides on... filling, capping and planarized is the way to go, however would tenting the opposite side be a issue..? note via hole size is 10mils... anyone aware of the IPC standard and or requirement..?
>
> Regard's, Frederick Dark Jr.
> Manager Senior PCB Designer
> Crestron Electronics, Inc.
> 22 Link Drive Rockleigh N.J. 07647
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