Unless you are needing true via in pad, e.g., a microvia going from layer 1-2 and or N-1 (which can be copper filled and these requirements are being worked on for the next revision of IPC-6012), then I agree with Karl about the loose tolerance on through vias. We ensure we design our pads large enough to support a specific minimum via drill diameter then we specify this minimum acceptable drill diameter on the drawing. After you have done your electrical and if necessary thermal calculations (if required), and you specify a minimum acceptable via drill diameter then you can add that the minimum finished size does not need to be measured and can be plated shut. The drill diameter should be verified by microsection of the "B" coupon holes.
There is also the copper filling of through vias or buried vias but there are limitations to diameter and aspect ratio. The end requirements are AABUS as they are not currently covered by a specification that I am aware of. As William states, there are board suppliers performing this process with success.
Regards,
Scott A. Bowles
Staff Engineer - Printed Circuit Designer IV
Engineering Services
L3 Fuzing & Ordnance Systems
3975 McMann Rd.
Cincinnati, OH 45245
Office: 513-943-2483
Mobile: 513-208-9009
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-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Karl Bates
Sent: Friday, September 12, 2014 11:24 AM
To: [log in to unmask]
Subject: Re: [DC] Vias
Be very careful about specifying loose tolerances on your vias ! If you have calculated the current capability or thermal transfer of that via, and your vendor decides to use a .008 finished instead of a .012 finished your product may not perform as expected.I use specific / unique via sizing if necessary, so they are not undersized.
Karl
> Date: Fri, 12 Sep 2014 10:29:38 -0400
> From: [log in to unmask]
> Subject: Re: [DC] Vias
> To: [log in to unmask]
>
> I was referring to the type of via that they plate solid with copper all the way thru...
> Maybe copper 'filled' is not the correct term for that type of via?
>
> Via Systems/DDI does this process... I believe... as do a few others...
>
> http://www.google.com/patents/US20080196935
>
> http://www.dowelectronicmaterials.com/products/printed_circuit_boards/
> hdi/microfill_thf.htm
>
>
>
> William Brooks, CID+
> Senior MTS (Contract)
> 2747 Loker Ave West
> Carlsbad, CA 92010-6603
> 760-930-7212
> Fax: 760.918.8332
> Mobile: 760.216.0170
> E-mail: [log in to unmask]
>
>
>
>
> -----Original Message-----
> From: Anderson, Veronika [mailto:[log in to unmask]]
> Sent: Thursday, September 11, 2014 3:58 PM
> To: (Designers Council Forum); Brooks, William
> Subject: RE: [DC] Vias
>
> Bill,
>
> Can you clarify your definition of "copper filled via"?
> As far as I know, there is no via filling material that can be called a "copper fill".
> As you mentioned, the thicker plating improves the thermal transfer and current carrying characteristics of via.
> I've seen the drawings with a note "vias can be plated shut".
> However, the conventional plating process cannot close the via completely - there is always an air gap in the middle.
> The Reverse Pulse Plating Process provides the "solid copper plated via". So far only a few PWB manufacturers do that.
> If you use a solid copper plated vias in your designs, please share a name of PCB manufacturer that builds your boards.
>
> Regards,
>
> Veronika Anderson C.I.D | Sr. Electrical/Mechanical Design Engineer |
> Excelitas Technologies
>
> Office: +1 626.967.9521 x 236
> 1330 East Cypress Street, Covina, CA 91724 USA
> [log in to unmask] www.excelitas.com
>
> -----Original Message-----
> From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of
> Brooks, William
> Sent: Thursday, September 11, 2014 9:31 AM
> To: [log in to unmask]
> Subject: Re: [DC] Vias
>
> Peter was talking with me about using vias in thermal pads and how some still leave an open aperture the size of the thermal pad for their solder paste...
> This can cause the solder paste when it melts to be wicked down the via holes starving the part for solder... depending on the diameter of the vias and how many there are...
> One method to reduce this effect is to change the stencil aperture to a pattern that avoids the vias and helps distribute the paste over the thermal pad area evenly...
> See this illustration by Texas Instruments...
>
> http://www.ti.com/ods/images/SNLS302D/sample_layout_DAP_snls302.png
>
> Another thing that helps is to reduce the diameter of the via to reduce its wicking volume... smaller holes wick less...
> I have used .008 in. diameter vias for that purpose before...
>
> Or... you can have the via holes filled and planarized... thus no extra solder is wicked down the holes...
> Partial filling tends to cause problems...
> For example: Trapped gases will expand in the high heat of the reflow oven and cause solder balls to occur...
> This is bad for your design when installed in the electronics application it typically must work in because solder balls are conductive and can cause shorts between pins and exposed pads or get loose in vibration and bounce around to other assemblies and cause the same sort of problems.
>
> Also I have found that filling vias with solder does not improve their thermal transfer characteristics very much... Solder is not that great a heat conductor. Copper is the best thermal conductor typically for our PCB applications... so thicker copper plating in the holes or copper filled vias are bound to be far superior for thermal transfer reasons than filling the vias with solder.
>
>
>
> William Brooks, CID+
>
>
>
>
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