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September 2014

DesignerCouncil@IPC.ORG

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Subject:
From:
James Head <[log in to unmask]>
Reply To:
(Designers Council Forum)
Date:
Wed, 10 Sep 2014 17:11:04 +0100
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1) Certification agencies such as UL require two vias of no less than 0.35 mm diameter, or a single via of no less than 0.70 mm diameter for an infallible connection for intrinsic safety for equipment used in hazardous areas.  They request a note on the drawing specifying a 33 micron minimum PTH plating thickness.

2) I've found that different designers interpret IPC-2221 Section 9.1.1 in different ways.  Some will apply the equation for minimum land size being applied to vias where other designers see this as only applying to a PTH hole with a component lead.  I've had feedback from the IPC saying that it does apply to vias but I think this needs re-visiting and clarifying more clearly as I've seen 0.50 mm pad with a 0.25 mm drill recommended for vias which doesn't meet IPC-2221 Section 9.1.1.


Regards,

James



James Head BEng CID+ MIIE MIET
Senior PCB CAD Engineer
Crowcon Detection Instruments Limited
172 Brook Drive
Milton Park
OX4 4SD
Telephone: 01235 557700
E-mail: [log in to unmask]




-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Brooks, William
Sent: 10 September 2014 16:45
To: [log in to unmask]
Subject: [DC] Vias

I would like to revisit the subject of vias and some of the issues people have with them. 

There are many types and applications where vias are used in PCB designs. 

Here are a couple of the design issues I have seen. 

1) Large a diameter drilled vias... (Anything larger than .018in [0.45mm] diameter used for inter plane connections without a component lead)
   a) Do you plug your vias? Soldermask plug falls right thru..., There is not enough viscosity or surface tension to keep the uncured LPI in the plated hole when applied.
   b) Some like to use larger vias for more current carrying capacity... however, multiple smaller vias can be used... with some added benefits... 
   c) Multiple small vias can reduce inter-plane impedance by splitting the parallel impedance between the vias. 2 vias in parallel = half the total impedance created by a single via.
2) Not enough annular ring pad around the drilled via hole.
   a) A standard via, like .014 dia plated thru hole with a .026 dia pad can be made by any board shop without a cost adder. But... if you reduce the pad to .022 dia to save routing space they will have difficulty with hole pad breakout on larger boards... 

I have seen boards with .008 dia via holes with .013 dia pads made... but the yields were terrible on a 12X12 inch panel... and lots of breakout... this not a good practice if you want to make a low cost reliable board...  Typically I use .010 diameter vias with a .022 dia pad in most of my .062 thick designs... Typically that's about .012 in. over the diameter of the finished hole diameter. You can get away with .010 over the plated hole diameter on smaller boards with special handling of the boards... like no stack drilling, smaller area to reduce inner pad misalignment during lamination... etc. I have used .008 dia. Vias with .018 dia pads for dogbone breakout vias under BGAs with a pitch of 0.8mm. This worked but I had to keep the size of the board panel small... I don't like to drive the board manufacturer crazy... they tend to want to charge me a lot more... ;) Lower aspect ratios can improve yields.. can you go with a thinner board material? We need to understand the variables. 

What is the smallest practical low cost via then? And when should you use them? Most bare board manufacturers will advertise what the minimum via they can make, with great pride... be careful! This is not necessarily, what you want for your board... Most likely they will have some yield troubles...

I'd like to hear some comments on vias from other members of this forum... 

Largest vias
Smallest vias
Thermal vias
Micro vias
Laser vias
High aspect ratio vias
Filled vias
Blind vias
Buried vias
Stitch vias
Via in Pad
Vias used in RF applications
Proper placement of vias for decoupling



William Brooks, CID+

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